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[src/trunk]: src/sys add new cryptographic accelerator driver 'mvxpsec.'
details: https://anonhg.NetBSD.org/src/rev/5d6e4fa25de9
branches: trunk
changeset: 808799:5d6e4fa25de9
user: hsuenaga <hsuenaga%NetBSD.org@localhost>
date: Wed Jun 03 04:20:02 2015 +0000
description:
add new cryptographic accelerator driver 'mvxpsec.'
this driver controls CESA unit as same as mvcesa, but uses DMA engines and
does CBC operations, HMAC operations by hardware. about 2 kbytes of data
are processed at one. supported algorithms are:
- DES-CBC, 3DES-CBC, AES-CBC
- HMAC-SHA1, HMAC-MD5
non-CBC algorithm such as AES-GCM is not supported by CESA's acceleration
engine. mvcesa is still useful to implement such algorithms as combination of
accelerated block cipher and software chaining.
diffstat:
sys/arch/arm/marvell/files.marvell | 5 +-
sys/arch/arm/marvell/mvsoc.c | 38 +-
sys/arch/arm/marvell/mvsocvar.h | 4 +-
sys/dev/marvell/files.armada | 7 +-
sys/dev/marvell/mvxpsec.c | 3690 ++++++++++++++++++++++++++++++++++++
sys/dev/marvell/mvxpsecreg.h | 270 ++
sys/dev/marvell/mvxpsecvar.h | 511 ++++
7 files changed, 4520 insertions(+), 5 deletions(-)
diffs (truncated from 4656 to 300 lines):
diff -r a52f120f9635 -r 5d6e4fa25de9 sys/arch/arm/marvell/files.marvell
--- a/sys/arch/arm/marvell/files.marvell Wed Jun 03 04:00:06 2015 +0000
+++ b/sys/arch/arm/marvell/files.marvell Wed Jun 03 04:20:02 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.marvell,v 1.16 2015/06/03 03:55:47 hsuenaga Exp $
+# $NetBSD: files.marvell,v 1.17 2015/06/03 04:20:02 hsuenaga Exp $
#
# Configuration info for Marvell System on Chip support
#
@@ -70,6 +70,9 @@
# Cryptographic Engines and Security Accelerator
attach mvcesa at mvsoc with mvcesa_mbus
+# ARMADA XP Cryptographic Engines and Security Accelerator
+attach mvxpsec at mvsoc with mvxpsec_mbus
+
# TWSI Two-Wire Serial Interface
attach gttwsi at mvsoc with gttwsi_mbus
diff -r a52f120f9635 -r 5d6e4fa25de9 sys/arch/arm/marvell/mvsoc.c
--- a/sys/arch/arm/marvell/mvsoc.c Wed Jun 03 04:00:06 2015 +0000
+++ b/sys/arch/arm/marvell/mvsoc.c Wed Jun 03 04:20:02 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $ */
+/* $NetBSD: mvsoc.c,v 1.23 2015/06/03 04:20:02 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
* All rights reserved.
@@ -26,12 +26,13 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.23 2015/06/03 04:20:02 hsuenaga Exp $");
#include "opt_cputypes.h"
#include "opt_mvsoc.h"
#ifdef ARMADAXP
#include "mvxpe.h"
+#include "mvxpsec.h"
#endif
#include <sys/param.h>
@@ -274,6 +275,10 @@
ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 },
{ ARMADAXP_TAG_PEX3_IO,
ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 },
+ { ARMADAXP_TAG_CRYPT0,
+ ARMADAXP_ATTR_CRYPT0_NOSWAP, ARMADAXP_UNITID_CRYPT },
+ { ARMADAXP_TAG_CRYPT1,
+ ARMADAXP_ATTR_CRYPT1_NOSWAP, ARMADAXP_UNITID_CRYPT },
#endif
};
@@ -692,8 +697,13 @@
{ ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC > 0
+ { ARMADAXP(MV78130), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+ { ARMADAXP(MV78130), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 },
+#else
{ ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
{ ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
+#endif
{ ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -728,8 +738,13 @@
{ ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC > 0
+ { ARMADAXP(MV78160), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+ { ARMADAXP(MV78160), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 },
+#else
{ ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
{ ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
+#endif
{ ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -762,8 +777,13 @@
{ ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC > 0
+ { ARMADAXP(MV78230), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+ { ARMADAXP(MV78230), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 },
+#else
{ ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
{ ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
+#endif
{ ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -798,8 +818,13 @@
{ ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC > 0
+ { ARMADAXP(MV78260), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+ { ARMADAXP(MV78260), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 },
+#else
{ ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
{ ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
+#endif
{ ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -835,8 +860,13 @@
{ ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC > 0
+ { ARMADAXP(MV78460), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+ { ARMADAXP(MV78460), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 },
+#else
{ ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
{ ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
+#endif
{ ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -861,8 +891,12 @@
{ ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT },
{ ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC > 0
+ { ARMADA370(MV6710), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+#else
{ ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
#endif
+#endif
};
diff -r a52f120f9635 -r 5d6e4fa25de9 sys/arch/arm/marvell/mvsocvar.h
--- a/sys/arch/arm/marvell/mvsocvar.h Wed Jun 03 04:00:06 2015 +0000
+++ b/sys/arch/arm/marvell/mvsocvar.h Wed Jun 03 04:20:02 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocvar.h,v 1.9 2015/06/03 03:04:21 hsuenaga Exp $ */
+/* $NetBSD: mvsocvar.h,v 1.10 2015/06/03 04:20:02 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -119,6 +119,8 @@
ARMADAXP_TAG_PEX2_IO,
ARMADAXP_TAG_PEX3_MEM,
ARMADAXP_TAG_PEX3_IO,
+ ARMADAXP_TAG_CRYPT0,
+ ARMADAXP_TAG_CRYPT1,
};
int mvsoc_target(int, uint32_t *, uint32_t *, uint32_t *, uint32_t *);
int mvsoc_target_dump(struct mvsoc_softc *);
diff -r a52f120f9635 -r 5d6e4fa25de9 sys/dev/marvell/files.armada
--- a/sys/dev/marvell/files.armada Wed Jun 03 04:00:06 2015 +0000
+++ b/sys/dev/marvell/files.armada Wed Jun 03 04:20:02 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.armada,v 1.2 2015/06/03 03:55:47 hsuenaga Exp $
+# $NetBSD: files.armada,v 1.3 2015/06/03 04:20:02 hsuenaga Exp $
# Configuration info for Marvell ARMADA integrated peripherals
# ARMADA XP Buffer Manger
@@ -9,3 +9,8 @@
define mvxpe { [port = -1 ], [irq = -1] }
device mvxpe: mvxpbm, ether, ifnet, arp, mii
file dev/marvell/if_mvxpe.c mvxpe needs-flag
+
+# ARMADA XP Cryptographic Engines and Security Accelerator
+define mvxpsec { [port = -1 ], [irq = -1] }
+device mvxpsec: opencrypto
+file dev/marvell/mvxpsec.c mvxpsec needs-flag
diff -r a52f120f9635 -r 5d6e4fa25de9 sys/dev/marvell/mvxpsec.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/marvell/mvxpsec.c Wed Jun 03 04:20:02 2015 +0000
@@ -0,0 +1,3690 @@
+/* $NetBSD: mvxpsec.c,v 1.1 2015/06/03 04:20:02 hsuenaga Exp $ */
+/*
+ * Copyright (c) 2015 Internet Initiative Japan Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Cryptographic Engine and Security Accelerator(MVXPSEC)
+ */
+#include <sys/cdefs.h>
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/kernel.h>
+#include <sys/queue.h>
+#include <sys/conf.h>
+#include <sys/proc.h>
+#include <sys/bus.h>
+#include <sys/evcnt.h>
+#include <sys/device.h>
+#include <sys/endian.h>
+#include <sys/errno.h>
+#include <sys/kmem.h>
+#include <sys/mbuf.h>
+#include <sys/callout.h>
+#include <sys/pool.h>
+#include <sys/cprng.h>
+#include <sys/syslog.h>
+#include <sys/mutex.h>
+#include <sys/kthread.h>
+#include <sys/atomic.h>
+#include <sys/sha1.h>
+#include <sys/md5.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <crypto/rijndael/rijndael.h>
+
+#include <opencrypto/cryptodev.h>
+#include <opencrypto/xform.h>
+
+#include <net/net_stats.h>
+
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <netinet/ip6.h>
+
+#include <netipsec/esp_var.h>
+
+#include <arm/cpufunc.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/armadaxpreg.h>
+#include <dev/marvell/marvellreg.h>
+#include <dev/marvell/marvellvar.h>
+#include <dev/marvell/mvxpsecreg.h>
+#include <dev/marvell/mvxpsecvar.h>
+
+#ifdef DEBUG
+#define STATIC __attribute__ ((noinline)) extern
+#define _STATIC __attribute__ ((noinline)) extern
+#define INLINE __attribute__ ((noinline)) extern
+#define _INLINE __attribute__ ((noinline)) extern
+#else
+#define STATIC static
+#define _STATIC __attribute__ ((unused)) static
+#define INLINE static inline
+#define _INLINE __attribute__ ((unused)) static inline
+#endif
+
+/*
+ * IRQ and SRAM spaces for each of unit
+ * XXX: move to attach_args
+ */
+struct {
+ int err_int;
+} mvxpsec_config[] = {
+ { .err_int = ARMADAXP_IRQ_CESA0_ERR, }, /* unit 0 */
+ { .err_int = ARMADAXP_IRQ_CESA1_ERR, }, /* unit 1 */
+};
+#define MVXPSEC_ERR_INT(sc) \
+ mvxpsec_config[device_unit((sc)->sc_dev)].err_int
+
+/*
+ * AES
+ */
+#define MAXBC (128/32)
+#define MAXKC (256/32)
+#define MAXROUNDS 14
+STATIC int mv_aes_ksched(uint8_t[4][MAXKC], int,
+ uint8_t[MAXROUNDS+1][4][MAXBC]);
+STATIC int mv_aes_deckey(uint8_t *, uint8_t *, int);
+
+/*
+ * device driver autoconf interface
+ */
+STATIC int mvxpsec_match(device_t, cfdata_t, void *);
+STATIC void mvxpsec_attach(device_t, device_t, void *);
+STATIC void mvxpsec_evcnt_attach(struct mvxpsec_softc *);
+
+/*
+ * register setup
+ */
+STATIC int mvxpsec_wininit(struct mvxpsec_softc *, enum marvell_tags *);
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