[src/trunk]: src/sys/arch/arm Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cp...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2782767372b3
branches:  trunk
changeset: 808938:2782767372b3
user:      skrll <skrll%NetBSD.org@localhost>
date:      Tue Jun 09 08:08:14 2015 +0000

description:
Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7

Prompted by matt@

diffstat:

 sys/arch/arm/arm/cpufunc_asm_armv7.S |  19 -------------------
 sys/arch/arm/arm32/genassym.cf       |   5 ++++-
 sys/arch/arm/cortex/a9_mpsubr.S      |   6 +++---
 sys/arch/arm/include/armreg.h        |  18 +++++++++++++++++-
 sys/arch/arm/include/locore.h        |   7 +++++--
 5 files changed, 29 insertions(+), 26 deletions(-)

diffs (121 lines):

diff -r d5fd9d1233d7 -r 2782767372b3 sys/arch/arm/arm/cpufunc_asm_armv7.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S      Tue Jun 09 00:39:53 2015 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S      Tue Jun 09 08:08:14 2015 +0000
@@ -45,25 +45,6 @@
        bx      lr
 END(armv7_wait)
 
-
-#define        TTBR_C                  (1 << 0)
-#define        TTBR_S                  (1 << 1)
-#define        TTBR_IMP                (1 << 2)
-#define        TTBR_RGN_MASK           (3 << 3)
-#define         TTBR_RGN_NC            (0 << 3)
-#define         TTBR_RGN_WBWA          (1 << 3)
-#define         TTBR_RGN_WT            (2 << 3)
-#define         TTBR_RGN_WBNWA         (3 << 3)
-#define        TTBR_NOS                (1 << 5)
-#define        TTBR_IRGN_MASK          ((1 << 6) | (1 << 0))
-#define         TTBR_IRGN_NC           ((0 << 6) | (0 << 0))
-#define         TTBR_IRGN_WBWA         ((0 << 6) | (1 << 0))
-#define         TTBR_IRGN_WT           ((1 << 6) | (0 << 0))
-#define         TTBR_IRGN_WBNWA        ((1 << 6) | (1 << 0))
-
-#define        TTBR_UPATTR             (TTBR_S | TTBR_RGN_WBNWA | TTBR_C)
-#define        TTBR_MPATTR             (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA)
-
 ENTRY(armv7_context_switch)
        dsb                             @ data synchronization barrier
        mrc     p15, 0, ip, c0, c0, 5   @ get MPIDR
diff -r d5fd9d1233d7 -r 2782767372b3 sys/arch/arm/arm32/genassym.cf
--- a/sys/arch/arm/arm32/genassym.cf    Tue Jun 09 00:39:53 2015 +0000
+++ b/sys/arch/arm/arm32/genassym.cf    Tue Jun 09 08:08:14 2015 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: genassym.cf,v 1.72 2015/04/15 15:44:19 matt Exp $
+#      $NetBSD: genassym.cf,v 1.73 2015/06/09 08:08:14 skrll Exp $
 
 # Copyright (c) 1982, 1990 The Regents of the University of California.
 # All rights reserved.
@@ -138,6 +138,9 @@
 
 define TTBCR_S_N_1             __SHIFTIN(1, TTBCR_S_N)
 
+define TTBR_UPATTR             TTBR_UPATTR
+define TTBR_MPATTR             TTBR_MPATTR
+
 ifdef PMAP_INCLUDE_PTE_SYNC
 define PMAP_INCLUDE_PTE_SYNC   1
 endif
diff -r d5fd9d1233d7 -r 2782767372b3 sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Tue Jun 09 00:39:53 2015 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Tue Jun 09 08:08:14 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.41 2015/05/31 00:02:16 matt Exp $      */
+/*     $NetBSD: a9_mpsubr.S,v 1.42 2015/06/09 08:08:14 skrll Exp $     */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -198,8 +198,8 @@
        XPUTC(#'G')
        mrc     p15, 0, r1, c0, c0, 5   // MPIDR read
        cmp     r1, #0
-       orrlt   r10, r10, #0x5b         // MP, cachable (Normal WB)
-       orrge   r10, r10, #0x1b         // Non-MP, cacheable, normal WB
+       orrlt   r10, r10, #TTBR_MPATTR  // MP, cachable (Normal WB)
+       orrge   r10, r10, #TTBR_UPATTR  // Non-MP, cacheable, normal WB
        XPUTC(#'0')
        mcr     p15, 0, r10, c2, c0, 0  // TTBR0 write
 #if defined(ARM_MMU_EXTENDED)
diff -r d5fd9d1233d7 -r 2782767372b3 sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Tue Jun 09 00:39:53 2015 +0000
+++ b/sys/arch/arm/include/armreg.h     Tue Jun 09 08:08:14 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.106 2015/05/30 20:39:56 skrll Exp $       */
+/*     $NetBSD: armreg.h,v 1.107 2015/06/09 08:08:14 skrll Exp $       */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -645,6 +645,22 @@
 #define L2CTRL_NUMCPU  __BITS(25,24)   // numcpus - 1
 #define L2CTRL_ICPRES  __BIT(23)       // Interrupt Controller is present
 
+/* Translation Table Base Register */
+#define        TTBR_C                  __BIT(0)        /* without MPE */
+#define        TTBR_S                  __BIT(1)
+#define        TTBR_IMP                __BIT(2)
+#define        TTBR_RGN_MASK           __BITS(4,3)
+#define         TTBR_RGN_NC            __SHIFTIN(0, TTBR_RGN_MASK)
+#define         TTBR_RGN_WBWA          __SHIFTIN(1, TTBR_RGN_MASK)
+#define         TTBR_RGN_WT            __SHIFTIN(2, TTBR_RGN_MASK)
+#define         TTBR_RGN_WBNWA         __SHIFTIN(3, TTBR_RGN_MASK)
+#define        TTBR_NOS                __BIT(5)
+#define        TTBR_IRGN_MASK          (__BIT(6) | __BIT(0))
+#define         TTBR_IRGN_NC           0
+#define         TTBR_IRGN_WBWA         __BIT(6)
+#define         TTBR_IRGN_WT           __BIT(0)
+#define         TTBR_IRGN_WBNWA        (__BIT(0) | __BIT(6))
+
 /* Translate Table Base Control Register */
 #define TTBCR_S_EAE    __BIT(31)       // Extended Address Extension
 #define TTBCR_S_PD1    __BIT(5)        // Don't use TTBR1
diff -r d5fd9d1233d7 -r 2782767372b3 sys/arch/arm/include/locore.h
--- a/sys/arch/arm/include/locore.h     Tue Jun 09 00:39:53 2015 +0000
+++ b/sys/arch/arm/include/locore.h     Tue Jun 09 08:08:14 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.h,v 1.23 2015/05/28 21:52:36 matt Exp $ */
+/*     $NetBSD: locore.h,v 1.24 2015/06/09 08:08:14 skrll Exp $        */
 
 /*
  * Copyright (c) 1994-1996 Mark Brinicombe.
@@ -133,7 +133,10 @@
                ((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0)
 #endif
 
-
+/*
+ * Translation Table Base Register Share/Cache settings */
+#define        TTBR_UPATTR     (TTBR_S | TTBR_RGN_WBNWA | TTBR_C)
+#define        TTBR_MPATTR     (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA)
 
 /* The address of the vector page. */
 extern vaddr_t vector_page;