[src/trunk]: src/sys/arch/arm/arm32 Use tlb is variants for MULTIPROCESSOR

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/35e3dd83913f
branches:  trunk
changeset: 803149:35e3dd83913f
user:      matt <matt%NetBSD.org@localhost>
date:      Tue Oct 14 08:03:13 2014 +0000

description:
Use tlb is variants for MULTIPROCESSOR

diffstat:

 sys/arch/arm/arm32/arm32_tlb.c |  10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diffs (36 lines):

diff -r 1fda1ae39481 -r 35e3dd83913f sys/arch/arm/arm32/arm32_tlb.c
--- a/sys/arch/arm/arm32/arm32_tlb.c    Tue Oct 14 08:00:27 2014 +0000
+++ b/sys/arch/arm/arm32/arm32_tlb.c    Tue Oct 14 08:03:13 2014 +0000
@@ -27,7 +27,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.2 2014/04/11 02:39:03 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.3 2014/10/14 08:03:13 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -60,7 +60,11 @@
 {
        const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
        arm_dsb();
+#ifdef MULTIPROCESSOR
+       armreg_tlbiallis_write(0);
+#else
        armreg_tlbiall_write(0);
+#endif
        arm_isb();
        if (__predict_false(vivt_icache_p)) {
                if (arm_has_tlbiasid_p) {
@@ -107,7 +111,11 @@
        arm_dsb();
        va = trunc_page(va) | asid;
        for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
+#ifdef MULTIPROCESSOR
+               armreg_tlbimvais_write(va);
+#else
                armreg_tlbimva_write(va);
+#endif
                //armreg_tlbiall_write(asid);
        }
        arm_isb();