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[src/trunk]: src/sys/dev/pci Basic support for I219. It doesn't work on I219, ...
details: https://anonhg.NetBSD.org/src/rev/fff42cb045c5
branches: trunk
changeset: 815211:fff42cb045c5
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Fri May 06 08:56:20 2016 +0000
description:
Basic support for I219. It doesn't work on I219, so it's disabled.
diffstat:
sys/dev/pci/if_wm.c | 278 ++++++++++++++++++++++++++++++++++++++++++------
sys/dev/pci/if_wmreg.h | 23 +++-
sys/dev/pci/if_wmvar.h | 3 +-
3 files changed, 265 insertions(+), 39 deletions(-)
diffs (truncated from 834 to 300 lines):
diff -r f16c794d44a2 -r fff42cb045c5 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Fri May 06 07:45:53 2016 +0000
+++ b/sys/dev/pci/if_wm.c Fri May 06 08:56:20 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.391 2016/02/09 08:32:11 ozaki-r Exp $ */
+/* $NetBSD: if_wm.c,v 1.392 2016/05/06 08:56:20 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.391 2016/02/09 08:32:11 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.392 2016/05/06 08:56:20 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -146,8 +146,9 @@
#define WM_DEBUG_GMII 0x08
#define WM_DEBUG_MANAGE 0x10
#define WM_DEBUG_NVM 0x20
+#define WM_DEBUG_INIT 0x40
int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
- | WM_DEBUG_MANAGE | WM_DEBUG_NVM;
+ | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT;
#define DPRINTF(x, y) if (wm_debug & (x)) printf y
#else
@@ -334,6 +335,10 @@
bus_space_tag_t sc_flasht; /* flash registers space tag */
bus_space_handle_t sc_flashh; /* flash registers space handle */
bus_size_t sc_flashs; /* flash registers space size */
+ off_t sc_flashreg_offset; /*
+ * offset to flash registers from
+ * start of BAR
+ */
bus_dma_tag_t sc_dmat; /* bus DMA tag */
struct ethercom sc_ethercom; /* ethernet common data */
@@ -490,15 +495,19 @@
#define CSR_WRITE_FLUSH(sc) \
(void) CSR_READ((sc), WMREG_STATUS)
-#define ICH8_FLASH_READ32(sc, reg) \
- bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
-#define ICH8_FLASH_WRITE32(sc, reg, data) \
- bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
-
-#define ICH8_FLASH_READ16(sc, reg) \
- bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
-#define ICH8_FLASH_WRITE16(sc, reg, data) \
- bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
+#define ICH8_FLASH_READ32(sc, reg) \
+ bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, \
+ (reg) + sc->sc_flashreg_offset)
+#define ICH8_FLASH_WRITE32(sc, reg, data) \
+ bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, \
+ (reg) + sc->sc_flashreg_offset, (data))
+
+#define ICH8_FLASH_READ16(sc, reg) \
+ bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, \
+ (reg) + sc->sc_flashreg_offset)
+#define ICH8_FLASH_WRITE16(sc, reg, data) \
+ bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, \
+ (reg) + sc->sc_flashreg_offset, (data))
#define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x)))
#define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x)))
@@ -688,10 +697,12 @@
static int32_t wm_ich8_cycle_init(struct wm_softc *);
static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
- uint16_t *);
+ uint32_t *);
static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
+static int32_t wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
+static int wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
/* iNVM */
static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
@@ -732,7 +743,7 @@
static bool wm_phy_resetisblocked(struct wm_softc *);
static void wm_get_hw_control(struct wm_softc *);
static void wm_release_hw_control(struct wm_softc *);
-static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int);
+static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
static void wm_smbustopci(struct wm_softc *);
static void wm_init_manageability(struct wm_softc *);
static void wm_release_manageability(struct wm_softc *);
@@ -1282,6 +1293,20 @@
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3,
"I218 LM Ethernet Connection",
WM_T_PCH_LPT, WMP_F_COPPER },
+#if 0
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V,
+ "I219 V Ethernet Connection",
+ WM_T_PCH_SPT, WMP_F_COPPER },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2,
+ "I219 V Ethernet Connection",
+ WM_T_PCH_SPT, WMP_F_COPPER },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM,
+ "I219 LM Ethernet Connection",
+ WM_T_PCH_SPT, WMP_F_COPPER },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2,
+ "I219 LM Ethernet Connection",
+ WM_T_PCH_SPT, WMP_F_COPPER },
+#endif
{ 0, 0,
NULL,
0, 0 },
@@ -1710,7 +1735,8 @@
&& (sc->sc_type != WM_T_ICH10)
&& (sc->sc_type != WM_T_PCH)
&& (sc->sc_type != WM_T_PCH2)
- && (sc->sc_type != WM_T_PCH_LPT)) {
+ && (sc->sc_type != WM_T_PCH_LPT)
+ && (sc->sc_type != WM_T_PCH_SPT)) {
/* ICH* and PCH* have no PCIe capability registers */
if (pci_get_capability(pa->pa_pc, pa->pa_tag,
PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
@@ -1799,7 +1825,7 @@
/* get PHY control from SMBus to PCIe */
if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
- || (sc->sc_type == WM_T_PCH_LPT))
+ || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT))
wm_smbustopci(sc);
/* Reset the chip to a known state. */
@@ -1910,6 +1936,22 @@
sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);
sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
+ sc->sc_flashreg_offset = 0;
+ break;
+ case WM_T_PCH_SPT:
+ /* SPT has no GFPREG; flash registers mapped through BAR0 */
+ sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF;
+ sc->sc_flasht = sc->sc_st;
+ sc->sc_flashh = sc->sc_sh;
+ sc->sc_ich8_flash_base = 0;
+ sc->sc_nvm_wordsize =
+ (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
+ * NVM_SIZE_MULTIPLIER;
+ /* It is size in bytes, we want words */
+ sc->sc_nvm_wordsize /= 2;
+ /* assume 2 banks */
+ sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
+ sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
break;
case WM_T_I210:
case WM_T_I211:
@@ -2030,6 +2072,7 @@
case WM_T_PCH:
case WM_T_PCH2:
case WM_T_PCH_LPT:
+ case WM_T_PCH_SPT:
/* Non-AMT based hardware can now take control from firmware */
if ((sc->sc_flags & WM_F_HAS_AMT) == 0)
wm_get_hw_control(sc);
@@ -2121,6 +2164,7 @@
case WM_T_PCH:
case WM_T_PCH2:
case WM_T_PCH_LPT:
+ case WM_T_PCH_SPT:
/* XXX The funcid should be checked on some devices */
apme_mask = WUC_APME;
eeprom_data = CSR_READ(sc, WMREG_WUC);
@@ -2237,7 +2281,7 @@
if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
|| sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
|| sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
- || sc->sc_type == WM_T_82573
+ || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573
|| sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
/* STATUS_TBIMODE reserved/reused, can't rely on it */
wm_gmii_mediainit(sc, wmp->wmp_product);
@@ -2376,6 +2420,7 @@
case WM_T_ICH10:
case WM_T_PCH2: /* PCH2 supports 9K frame size */
case WM_T_PCH_LPT:
+ case WM_T_PCH_SPT:
/* XXX limited to 9234 */
sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
break;
@@ -2783,6 +2828,8 @@
struct sockaddr_dl *sdl;
int s, error;
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(sc->sc_dev), __func__));
#ifndef WM_MPSAFE
s = splnet();
#endif
@@ -3000,7 +3047,8 @@
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
- || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
+ || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
+ || (sc->sc_type == WM_T_PCH_SPT)) {
hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
(((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
return (hash & 0x3ff);
@@ -3027,6 +3075,8 @@
uint32_t hash, reg, bit;
int i, size, ralmax;
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(sc->sc_dev), __func__));
if (sc->sc_type >= WM_T_82544)
mta_reg = WMREG_CORDOVA_MTA;
else
@@ -3052,7 +3102,7 @@
size = WM_RAL_TABSIZE_ICH8;
else if (sc->sc_type == WM_T_PCH2)
size = WM_RAL_TABSIZE_PCH2;
- else if (sc->sc_type == WM_T_PCH_LPT)
+ else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT))
size = WM_RAL_TABSIZE_PCH_LPT;
else if (sc->sc_type == WM_T_82575)
size = WM_RAL_TABSIZE_82575;
@@ -3064,7 +3114,7 @@
size = WM_RAL_TABSIZE;
wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
- if (sc->sc_type == WM_T_PCH_LPT) {
+ if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
switch (i) {
case 0:
@@ -3088,7 +3138,8 @@
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
- || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
+ || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
+ || (sc->sc_type == WM_T_PCH_SPT))
size = WM_ICH8_MC_TABSIZE;
else
size = WM_MC_TABSIZE;
@@ -3116,7 +3167,8 @@
if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
|| (sc->sc_type == WM_T_PCH2)
- || (sc->sc_type == WM_T_PCH_LPT))
+ || (sc->sc_type == WM_T_PCH_LPT)
+ || (sc->sc_type == WM_T_PCH_SPT))
reg &= 0x1f;
else
reg &= 0x7f;
@@ -3156,6 +3208,9 @@
static void
wm_set_vlan(struct wm_softc *sc)
{
+
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(sc->sc_dev), __func__));
/* Deal with VLAN enables. */
if (VLAN_ATTACHED(&sc->sc_ethercom))
sc->sc_ctrl |= CTRL_VME;
@@ -3245,6 +3300,7 @@
case WM_T_PCH:
case WM_T_PCH2:
case WM_T_PCH_LPT:
+ case WM_T_PCH_SPT:
for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
reg = CSR_READ(sc, WMREG_STATUS);
if ((reg & STATUS_LAN_INIT_DONE) != 0)
@@ -3327,6 +3383,7 @@
case WM_T_PCH:
case WM_T_PCH2:
case WM_T_PCH_LPT:
+ case WM_T_PCH_SPT:
delay(10*1000);
if (sc->sc_type >= WM_T_ICH10)
wm_lan_init_done(sc);
@@ -3350,6 +3407,8 @@
{
uint32_t tarc0, tarc1, reg;
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(sc->sc_dev), __func__));
/* For 82571 variant, 80003 and ICHs */
if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583))
|| (sc->sc_type >= WM_T_80003)) {
@@ -3572,6 +3631,8 @@
int i, error = 0;
uint32_t reg, mask;
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(sc->sc_dev), __func__));
/*
* Allocate on-chip memory according to the MTU size.
* The Packet Buffer Allocation register must be written
@@ -3630,6 +3691,7 @@
case WM_T_PCH:
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