[src/trunk]: src/sys/dev/pci Add new PCIE_HAS_LINKREGS(pcie_devtype) and use ...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/54872da196e0
branches:  trunk
changeset: 837355:54872da196e0
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Nov 30 10:18:37 2018 +0000

description:
Add new PCIE_HAS_LINKREGS(pcie_devtype) and use it. No functional change.

diffstat:

 sys/dev/pci/pci_subr.c |  11 ++++-------
 sys/dev/pci/pcireg.h   |   9 ++++++++-
 2 files changed, 12 insertions(+), 8 deletions(-)

diffs (79 lines):

diff -r b9e0da1ca4f8 -r 54872da196e0 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c    Fri Nov 30 09:53:40 2018 +0000
+++ b/sys/dev/pci/pci_subr.c    Fri Nov 30 10:18:37 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci_subr.c,v 1.209 2018/11/30 09:05:35 msaitoh Exp $   */
+/*     $NetBSD: pci_subr.c,v 1.210 2018/11/30 10:18:37 msaitoh Exp $   */
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.209 2018/11/30 09:05:35 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.210 2018/11/30 10:18:37 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -1756,7 +1756,6 @@
 {
        pcireg_t reg; /* for each register */
        pcireg_t val; /* for each bitfield */
-       bool check_link = true;
        bool check_slot = false;
        unsigned int pcie_devtype;
        bool check_upstreamport = false;
@@ -1803,11 +1802,9 @@
                break;
        case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
                printf("Root Complex Integrated Endpoint\n");
-               check_link = false;
                break;
        case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
                printf("Root Complex Event Collector\n");
-               check_link = false;
                break;
        default:
                printf("unknown\n");
@@ -1884,7 +1881,7 @@
        onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);
        onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD);
 
-       if (check_link) {
+       if (PCIE_HAS_LINKREGS(pcie_devtype)) {
                /* Link Capability Register */
                reg = regs[o2i(capoff + PCIE_LCAP)];
                printf("    Link Capabilities Register: 0x%08x\n", reg);
@@ -2235,7 +2232,7 @@
        }
        onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);
 
-       if (check_link) {
+       if (PCIE_HAS_LINKREGS(pcie_devtype)) {
                bool drs_supported = false;
 
                /* Link Capability 2 */
diff -r b9e0da1ca4f8 -r 54872da196e0 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Fri Nov 30 09:53:40 2018 +0000
+++ b/sys/dev/pci/pcireg.h      Fri Nov 30 10:18:37 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.145 2018/11/30 09:05:35 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.146 2018/11/30 10:18:37 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -1153,6 +1153,13 @@
 #define PCIE_SLCAP2    0x34    /* Slot Capabilities 2 Register */
 #define PCIE_SLCSR2    0x38    /* Slot Control & Status 2 Register */
 
+/*
+ * Other than Root Complex Integrated Endpoint and Root Complex Event Collector
+ * have link related registers.
+ */
+#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_ROOT_INTEP) && \
+           ((type) != PCIE_XCAP_TYPE_ROOT_EVNTC))
+
 /* Only root port and root complex event collector have PCIE_RCR & PCIE_RSR */
 #define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_ROOT) || \
            ((type) == PCIE_XCAP_TYPE_ROOT_EVNTC))