[src/trunk]: src/sys/arch/x86/include Add Intel CPUID Extended Topology Enume...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f0cbd688227b
branches:  trunk
changeset: 837157:f0cbd688227b
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Wed Nov 21 12:18:53 2018 +0000

description:
Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.

diffstat:

 sys/arch/x86/include/specialreg.h |  19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)

diffs (33 lines):

diff -r 83e6cf348300 -r f0cbd688227b sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Wed Nov 21 11:44:26 2018 +0000
+++ b/sys/arch/x86/include/specialreg.h Wed Nov 21 12:18:53 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.133 2018/11/21 06:09:49 msaitoh Exp $ */
+/*     $NetBSD: specialreg.h,v 1.134 2018/11/21 12:18:53 msaitoh Exp $ */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -415,6 +415,23 @@
        "\35" "L1D_FLUSH" "\36" "ARCH_CAP"              "\40" "SSBD"
 
 /*
+ * Intel CPUID Extended Topology Enumeration Fn0000000b
+ * %ecx == level number
+ *     %eax: See below.
+ *     %ebx: Number of logical processors at this level.
+ *     %ecx: See below.
+ *     %edx: x2APIC ID of the current logical processor.
+ */
+/* %eax */
+#define CPUID_TOP_SHIFTNUM     __BITS(4, 0) /* Topology ID shift value */
+/* %ecx */
+#define CPUID_TOP_LVLNUM       __BITS(7, 0) /* Level number */
+#define CPUID_TOP_LVLTYPE      __BITS(15, 8) /* Level type */
+#define CPUID_TOP_LVLTYPE_INVAL        0               /* Invalid */
+#define CPUID_TOP_LVLTYPE_SMT  1               /* SMT */
+#define CPUID_TOP_LVLTYPE_CORE 2               /* Core */
+
+/*
  * Intel/AMD CPUID Processor extended state Enumeration Fn0000000d
  *
  * %ecx == 0: supported features info: