[src/trunk]: src/sys/arch/mips/mips Set the cause register to zero after disa...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f0ca490ab1e9
branches:  trunk
changeset: 816801:f0ca490ab1e9
user:      skrll <skrll%NetBSD.org@localhost>
date:      Tue Jul 26 05:52:55 2016 +0000

description:
Set the cause register to zero after disabling interrupts now that spl0
doesn't do it.

My cobalt now boots (again again)

diffstat:

 sys/arch/mips/mips/locore.S |  4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diffs (18 lines):

diff -r d3d0d76ec467 -r f0ca490ab1e9 sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S       Tue Jul 26 04:18:04 2016 +0000
+++ b/sys/arch/mips/mips/locore.S       Tue Jul 26 05:52:55 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.202 2016/07/11 16:15:36 matt Exp $        */
+/*     $NetBSD: locore.S,v 1.203 2016/07/26 05:52:55 skrll Exp $       */
 
 /*
  * Copyright (c) 1992, 1993
@@ -97,6 +97,8 @@
        mtc0    zero, MIPS_COP_0_STATUS         # Disable interrupts
        COP0_SYNC
 #endif
+       mtc0    zero, MIPS_COP_0_CAUSE
+       COP0_SYNC
 #ifdef MIPS64_OCTEON
        //
        // U-boot on the erlite starts all cpus at the kernel entry point.