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[src/netbsd-7]: src/sys Pull up following revision(s) (requested by snj in ti...
details: https://anonhg.NetBSD.org/src/rev/18665bb1e0e2
branches: netbsd-7
changeset: 799092:18665bb1e0e2
user: riz <riz%NetBSD.org@localhost>
date: Tue Mar 17 17:52:48 2015 +0000
description:
Pull up following revision(s) (requested by snj in ticket #590):
sys/external/bsd/drm2/i915drm/intel_gtt.c: revision 1.5
sys/external/bsd/drm2/drm/drm_drv.c: revision 1.15
sys/external/bsd/drm2/dist/drm/i915/i915_gem.c: revision 1.28
sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_nv50.c: revision 1.3
sys/dev/pci/agp_i810.c: revision 1.115
sys/dev/pci/agp_i810.c: revision 1.116
sys/external/bsd/drm2/include/drm/intel-gtt.h: revision 1.5
sys/dev/pci/agp_i810.c: revision 1.117
sys/external/bsd/drm2/drm/drm_gem_vm.c: revision 1.6
sys/dev/pci/agp_i810var.h: revision 1.6
Issue a write barrier after updating the GTT.
Linux never used to do this...until a month:
<a rel="nofollow" href="https://bugs.freedesktop.org/show_bug.cgi?id=88191";>https://bugs.freedesktop.org/show_bug.cgi?id=88191</a>
commit 983d308cb8f602d1920a8c40196eb2ab6cc07bd2
Author: Chris Wilson <chris%chris-wilson.co.uk@localhost>
Date: Mon Jan 26 10:47:10 2015 +0000
agp/intel: Serialise after GTT updates
Include <sys/atomic.h> for membar_producer.
(Why didn't this fail in my build?)
Pass cache-related flags through to the GTT on pre-SNB devices.
I had assumed for ages this would increase the amount of caching and
thereby increase the chance of stale caches leading to rendering
glitches. But apparently I was wrong, and failing to pass these
through was causing all sorts of problems!
Dedup the NetBSD portion of the code (ok Riastradh), no functional change.
Don't return events that are too large and leave them in the list.
Apply access control to gem mmap.
fix gcc is stupid.
diffstat:
sys/dev/pci/agp_i810.c | 46 ++-
sys/dev/pci/agp_i810var.h | 9 +-
sys/external/bsd/drm2/dist/drm/i915/i915_gem.c | 106 ++-------
sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_nv50.c | 6 +-
sys/external/bsd/drm2/drm/drm_drv.c | 6 +-
sys/external/bsd/drm2/drm/drm_gem_vm.c | 9 +-
sys/external/bsd/drm2/i915drm/intel_gtt.c | 21 +-
sys/external/bsd/drm2/include/drm/intel-gtt.h | 12 +-
8 files changed, 93 insertions(+), 122 deletions(-)
diffs (truncated from 507 to 300 lines):
diff -r 620636a6cbe2 -r 18665bb1e0e2 sys/dev/pci/agp_i810.c
--- a/sys/dev/pci/agp_i810.c Mon Mar 16 18:59:54 2015 +0000
+++ b/sys/dev/pci/agp_i810.c Tue Mar 17 17:52:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: agp_i810.c,v 1.112.2.1 2014/09/18 10:25:33 martin Exp $ */
+/* $NetBSD: agp_i810.c,v 1.112.2.2 2015/03/17 17:52:49 riz Exp $ */
/*-
* Copyright (c) 2000 Doug Rabson
@@ -30,10 +30,11 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.112.2.1 2014/09/18 10:25:33 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.112.2.2 2015/03/17 17:52:49 riz Exp $");
#include <sys/param.h>
#include <sys/systm.h>
+#include <sys/atomic.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/proc.h>
@@ -119,15 +120,23 @@
};
int
-agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v)
+agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off,
+ bus_addr_t addr, int flags)
{
u_int32_t pte;
- /* Bits 11:4 (physical start address extension) should be zero. */
- if ((v & 0xff0) != 0)
+ /*
+ * Bits 11:4 (physical start address extension) should be zero.
+ * Flag bits 3:0 should be zero too.
+ *
+ * XXX This should be a kassert -- no reason for this routine
+ * to allow failure.
+ */
+ if ((addr & 0xfff) != 0)
return EINVAL;
+ KASSERT(flags == (flags & 0x7));
- pte = (u_int32_t)v;
+ pte = (u_int32_t)addr;
/*
* We need to massage the pte if bus_addr_t is wider than 32 bits.
* The compiler isn't smart enough, hence the casts to uintmax_t.
@@ -137,17 +146,17 @@
if (isc->chiptype == CHIP_I965 ||
isc->chiptype == CHIP_G33 ||
isc->chiptype == CHIP_G4X) {
- if (((uintmax_t)v >> 36) != 0)
+ if (((uintmax_t)addr >> 36) != 0)
return EINVAL;
- pte |= (v >> 28) & 0xf0;
+ pte |= (addr >> 28) & 0xf0;
} else {
- if (((uintmax_t)v >> 32) != 0)
+ if (((uintmax_t)addr >> 32) != 0)
return EINVAL;
}
}
bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,
- 4*(off >> AGP_PAGE_SHIFT), pte);
+ 4*(off >> AGP_PAGE_SHIFT), pte | flags);
return 0;
}
@@ -156,6 +165,13 @@
agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off)
{
+ /*
+ * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>.
+ * Out of paranoia, let's do the write barrier and posting
+ * read, because I don't have enough time or hardware to
+ * conduct conclusive tests.
+ */
+ membar_producer();
(void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh,
4*(off >> AGP_PAGE_SHIFT));
}
@@ -1120,7 +1136,8 @@
}
}
- return agp_i810_write_gtt_entry(isc, offset, physical | 1);
+ return agp_i810_write_gtt_entry(isc, offset, physical,
+ AGP_I810_GTT_VALID);
}
static int
@@ -1138,7 +1155,7 @@
}
}
- return agp_i810_write_gtt_entry(isc, offset, 0);
+ return agp_i810_write_gtt_entry(isc, offset, 0, 0);
}
/*
@@ -1314,9 +1331,6 @@
return 0;
}
-#define I810_GTT_PTE_VALID 0x01
-#define I810_GTT_PTE_DCACHE 0x02
-
static int
agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem,
off_t offset)
@@ -1330,7 +1344,7 @@
KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0);
for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
error = agp_i810_write_gtt_entry(isc, offset + i,
- i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE);
+ i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE);
if (error)
goto fail0;
}
diff -r 620636a6cbe2 -r 18665bb1e0e2 sys/dev/pci/agp_i810var.h
--- a/sys/dev/pci/agp_i810var.h Mon Mar 16 18:59:54 2015 +0000
+++ b/sys/dev/pci/agp_i810var.h Tue Mar 17 17:52:48 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: agp_i810var.h,v 1.5 2014/06/10 14:00:56 riastradh Exp $ */
+/* $NetBSD: agp_i810var.h,v 1.5.2.1 2015/03/17 17:52:49 riz Exp $ */
/*-
* Copyright (c) 2000 Doug Rabson
@@ -67,6 +67,11 @@
extern struct agp_softc *agp_i810_sc;
-int agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, bus_addr_t);
+#define AGP_I810_GTT_VALID 0x01
+#define AGP_I810_GTT_I810_DCACHE 0x02 /* i810-only */
+#define AGP_I810_GTT_CACHED 0x06 /* >=i830 */
+
+int agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, bus_addr_t,
+ int);
void agp_i810_post_gtt_entry(struct agp_i810_softc *, off_t);
void agp_i810_chipset_flush(struct agp_i810_softc *);
diff -r 620636a6cbe2 -r 18665bb1e0e2 sys/external/bsd/drm2/dist/drm/i915/i915_gem.c
--- a/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c Mon Mar 16 18:59:54 2015 +0000
+++ b/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c Tue Mar 17 17:52:48 2015 +0000
@@ -705,51 +705,21 @@
offset = args->offset;
#ifdef __NetBSD__
- /*
- * XXX This is a big #ifdef with a lot of duplicated code, but
- * factoring out the loop head -- which is all that
- * substantially differs -- is probably more trouble than it's
- * worth at the moment.
- */
- while (0 < remain) {
- /* Get the next page. */
- shmem_page_offset = offset_in_page(offset);
- KASSERT(shmem_page_offset < PAGE_SIZE);
- page_length = MIN(remain, (PAGE_SIZE - shmem_page_offset));
+ while (0 < remain)
+#else
+ for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
+ offset >> PAGE_SHIFT)
+#endif
+ {
+#ifdef __NetBSD__
struct page *const page = i915_gem_object_get_page(obj,
atop(offset));
-
- /* Decide whether to swizzle bit 17. */
- page_do_bit17_swizzling = obj_do_bit17_swizzling &&
- (page_to_phys(page) & (1 << 17)) != 0;
-
- /* Try the fast path. */
- ret = shmem_pread_fast(page, shmem_page_offset, page_length,
- user_data, page_do_bit17_swizzling, needs_clflush);
- if (ret == 0)
- goto next_page;
-
- /* Fast path failed. Try the slow path. */
- mutex_unlock(&dev->struct_mutex);
- /* XXX prefault */
- ret = shmem_pread_slow(page, shmem_page_offset, page_length,
- user_data, page_do_bit17_swizzling, needs_clflush);
- mutex_lock(&dev->struct_mutex);
- if (ret)
- goto out;
-
-next_page: KASSERT(page_length <= remain);
- remain -= page_length;
- user_data += page_length;
- offset += page_length;
- }
#else
- for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
- offset >> PAGE_SHIFT) {
struct page *page = sg_page_iter_page(&sg_iter);
if (remain <= 0)
break;
+#endif
/* Operation in this page
*
@@ -771,7 +741,7 @@
goto next_page;
mutex_unlock(&dev->struct_mutex);
-
+#ifndef __NetBSD__
if (likely(!i915.prefault_disable) && !prefaulted) {
ret = fault_in_multipages_writeable(user_data, remain);
/* Userspace is tricking us, but we've already clobbered
@@ -781,7 +751,7 @@
(void)ret;
prefaulted = 1;
}
-
+#endif
ret = shmem_pread_slow(page, shmem_page_offset, page_length,
user_data, page_do_bit17_swizzling,
needs_clflush);
@@ -796,7 +766,6 @@
user_data += page_length;
offset += page_length;
}
-#endif
out:
i915_gem_object_unpin_pages(obj);
@@ -1050,6 +1019,9 @@
int needs_clflush_before = 0;
#ifndef __NetBSD__
struct sg_page_iter sg_iter;
+ int flush_mask = boot_cpu_data.x86_clflush_size - 1;
+#else
+ int flush_mask = cpu_info_primary.ci_cflush_lsize - 1;
#endif
user_data = to_user_ptr(args->data_ptr);
@@ -1083,48 +1055,18 @@
obj->dirty = 1;
#ifdef __NetBSD__
- while (0 < remain) {
- /* Get the next page. */
- shmem_page_offset = offset_in_page(offset);
- KASSERT(shmem_page_offset < PAGE_SIZE);
- page_length = MIN(remain, (PAGE_SIZE - shmem_page_offset));
+ while (0 < remain)
+#else
+ for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
+ offset >> PAGE_SHIFT)
+#endif
+ {
+#ifdef __NetBSD__
struct page *const page = i915_gem_object_get_page(obj,
atop(offset));
-
- /* Decide whether to flush the cache or swizzle bit 17. */
- const bool partial_cacheline_write = needs_clflush_before &&
- ((shmem_page_offset | page_length)
- & (cpu_info_primary.ci_cflush_lsize - 1));
- page_do_bit17_swizzling = obj_do_bit17_swizzling &&
- (page_to_phys(page) & (1 << 17)) != 0;
-
- /* Try the fast path. */
- ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
- user_data, page_do_bit17_swizzling,
- partial_cacheline_write, needs_clflush_after);
- if (ret == 0)
- goto next_page;
-
- /* Fast path failed. Try the slow path. */
- hit_slowpath = 1;
- mutex_unlock(&dev->struct_mutex);
- ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
- user_data, page_do_bit17_swizzling,
- partial_cacheline_write, needs_clflush_after);
- mutex_lock(&dev->struct_mutex);
- if (ret)
- goto out;
-
-next_page: KASSERT(page_length <= remain);
- remain -= page_length;
- user_data += page_length;
- offset += page_length;
- }
#else
- for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
- offset >> PAGE_SHIFT) {
struct page *page = sg_page_iter_page(&sg_iter);
- int partial_cacheline_write;
+#endif
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