[src/netbsd-7]: src/sys/arch/x86/pci Pull up following revision(s) (requested...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9956c5e939cd
branches:  netbsd-7
changeset: 798900:9956c5e939cd
user:      martin <martin%NetBSD.org@localhost>
date:      Mon Jan 26 16:16:11 2015 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #455):
        sys/arch/x86/pci/ichlpcib.c: revision 1.46

The PMBASE and GPIOBASE registers are not compatible with the PCI spec
and the map sizes are fixed to 128bytes. The pci_mapreg_submap()
function has a code to check the range of the BAR. The
PCI_MAPREG_IO_SIZE() macro returns lower than 128bytes on some
machines. This makes it impossible to use pci_mapreg_submap(). Use
pci_conf_read() and bus_space_map() directly.

diffstat:

 sys/arch/x86/pci/ichlpcib.c |  30 +++++++++++++++++++-----------
 1 files changed, 19 insertions(+), 11 deletions(-)

diffs (67 lines):

diff -r b81a39f34abe -r 9956c5e939cd sys/arch/x86/pci/ichlpcib.c
--- a/sys/arch/x86/pci/ichlpcib.c       Sun Jan 25 09:48:43 2015 +0000
+++ b/sys/arch/x86/pci/ichlpcib.c       Mon Jan 26 16:16:11 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ichlpcib.c,v 1.43.4.1 2015/01/08 11:39:38 martin Exp $ */
+/*     $NetBSD: ichlpcib.c,v 1.43.4.2 2015/01/26 16:16:11 martin Exp $ */
 
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -39,7 +39,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.43.4.1 2015/01/08 11:39:38 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.43.4.2 2015/01/26 16:16:11 martin Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -301,6 +301,7 @@
        struct pci_attach_args *pa = aux;
        struct lpcib_softc *sc = device_private(self);
        struct lpcib_device *lpcib_dev;
+       pcireg_t pmbase;
 
        sc->sc_pa = *pa;
 
@@ -322,12 +323,16 @@
         *
         * The PMBASE register is alike PCI BAR but not completely compatible
         * with it. The PMBASE define the base address and the type but
-        * not describe the size.
+        * not describe the size. The value of the register may be lower
+        * than LPCIB_PCI_PM_SIZE. It makes impossible to use
+        * pci_mapreg_submap() because the function does range check.
         */
-       if (pci_mapreg_submap(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0,
-               LPCIB_PCI_PM_SIZE, 0, &sc->sc_iot, &sc->sc_ioh, NULL,
-               &sc->sc_iosize)) {
-               aprint_error_dev(self, "can't map power management i/o space\n");
+       sc->sc_iot = pa->pa_iot;
+       pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE);
+       if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(pmbase),
+           LPCIB_PCI_PM_SIZE, 0, &sc->sc_ioh) != 0) {
+               aprint_error_dev(self,
+               "can't map power management i/o space\n");
                return;
        }
 
@@ -1080,11 +1085,14 @@
        /*
         * The GPIO_BASE register is alike PCI BAR but not completely
         * compatible with it. The PMBASE define the base address and the type
-        * but not describe the size.
+        * but not describe the size. The value of the register may be lower
+        * than LPCIB_PCI_GPIO_SIZE. It makes impossible to use
+        * pci_mapreg_submap() because the function does range check.
         */
-       rv = pci_mapreg_submap(&sc->sc_pa, base_reg, PCI_MAPREG_TYPE_IO, 0,
-           LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_iot, &sc->sc_gpio_ioh,
-           NULL, &sc->sc_gpio_ios);
+       sc->sc_gpio_iot = sc->sc_pa.pa_iot;
+       reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg);
+       rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg),
+           LPCIB_PCI_GPIO_SIZE, 0, &sc->sc_gpio_ioh);
        if (rv != 0) {
                aprint_error_dev(self, "can't map general purpose i/o space(rv = %d)\n", rv);
                return;