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[src/netbsd-7]: src Pull up following revision(s) (requested by jmcneill in t...
details: https://anonhg.NetBSD.org/src/rev/e3a301614f61
branches: netbsd-7
changeset: 799120:e3a301614f61
user: snj <snj%NetBSD.org@localhost>
date: Sat Mar 21 08:51:17 2015 +0000
description:
Pull up following revision(s) (requested by jmcneill in ticket #598):
sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9
sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4
sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3
sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1
sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7
sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1
sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5
sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7
sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9
sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1
sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3
sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_space.c: revision 1.1
sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8
sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1
sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8
sys/arch/arm/conf/files.arm: revision 1.129
sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17
sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29
sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12
sys/arch/arm/cortex/a9tmr_var.h: revision 1.4
sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4
sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7
sys/arch/arm/arm/cpufunc.c: revision 1.151
sys/arch/arm/include/bootconfig.h: revision 1.7
sys/arch/arm/include/locore.h: revision 1.19
sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17
sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2
sys/arch/evbarm/amlogic/genassym.cf: revision 1.1
sys/arch/evbarm/amlogic/platform.h: revision 1.1
sys/arch/evbarm/conf/files.amlogic: up to revision 1.8
sys/arch/evbarm/conf/std.amlogic: up to revision 1.2
sys/arch/evbarm/conf/mk.amlogic: revision 1.1
sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12
sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1
Don't use not as a variable since it's reserved in C++.
--
clean the a9 l2 cache before turning it on.
--
Add Cortex-A17 support
--
Fix CORTEXA17 support
--
Let the "cbar" device property override the cbar value, to work around
broken bootloaders
--
add a helper to update a9tmr frequency
--
detach and re-attach timecounter when updating freq, and reinit timer on
each cpu
--
fix typo
--
add BOOTOPT_TYPE_MACADDR for parsing mac address parameters
--
make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@
--
According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.
--
skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt
--
match on Cortex-A5
--
match on Cortex-A5
--
allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
--
print "A5" instead of "A9" at attach time if running on a Cortex-A5
--
Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
userland
--
Work-in-progress Odroid-C1 support.
--
no need to override ARM_CBAR, remove unused COM_16750 option
--
Add basic serial console support.
--
add dwctwo and usb devices
--
ODROID-C1 SMP support.
--
auto-detect RAM size
--
ODROID-C1 onboard ethernet support.
--
add amlogicrng, add commented-out genfb placeholder
--
enable amlogicsdhc
--
add ODROID-C1 install kernel
--
Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised
as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config
and make sure to set the correct speed before attaching CPUs.
The speed can still be scaled down with machdep.cpu sysctls.
--
disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM
--
Basic framebuffer console support. Work in progress.
diffstat:
etc/etc.evbarm/Makefile.inc | 4 +-
sys/arch/arm/amlogic/amlogic_board.c | 374 ++++++++++++++++
sys/arch/arm/amlogic/amlogic_canvasreg.h | 54 ++
sys/arch/arm/amlogic/amlogic_com.c | 445 +++++++++++++++++++
sys/arch/arm/amlogic/amlogic_comreg.h | 56 ++
sys/arch/arm/amlogic/amlogic_comvar.h | 37 +
sys/arch/arm/amlogic/amlogic_cpufreq.c | 279 ++++++++++++
sys/arch/arm/amlogic/amlogic_crureg.h | 136 ++++++
sys/arch/arm/amlogic/amlogic_dwctwo.c | 153 ++++++
sys/arch/arm/amlogic/amlogic_genfb.c | 389 +++++++++++++++++
sys/arch/arm/amlogic/amlogic_gmac.c | 114 +++++
sys/arch/arm/amlogic/amlogic_hdmireg.h | 38 +
sys/arch/arm/amlogic/amlogic_intr.h | 46 ++
sys/arch/arm/amlogic/amlogic_io.c | 143 ++++++
sys/arch/arm/amlogic/amlogic_reg.h | 92 ++++
sys/arch/arm/amlogic/amlogic_rng.c | 111 ++++
sys/arch/arm/amlogic/amlogic_sdhc.c | 599 ++++++++++++++++++++++++++
sys/arch/arm/amlogic/amlogic_sdhcreg.h | 150 ++++++
sys/arch/arm/amlogic/amlogic_space.c | 425 ++++++++++++++++++
sys/arch/arm/amlogic/amlogic_var.h | 91 ++++
sys/arch/arm/amlogic/amlogic_vpureg.h | 73 +++
sys/arch/arm/amlogic/files.amlogic | 60 ++
sys/arch/arm/arm/bootconfig.c | 30 +-
sys/arch/arm/conf/files.arm | 4 +-
sys/arch/arm/cortex/a9_mpsubr.S | 28 +-
sys/arch/arm/cortex/a9tmr.c | 45 +-
sys/arch/arm/cortex/a9tmr_var.h | 3 +-
sys/arch/arm/cortex/a9wdt.c | 17 +-
sys/arch/arm/cortex/armperiph.c | 9 +-
sys/arch/arm/cortex/pl310.c | 22 +-
sys/arch/arm/include/bootconfig.h | 3 +-
sys/arch/evbarm/amlogic/amlogic_machdep.c | 673 ++++++++++++++++++++++++++++++
sys/arch/evbarm/amlogic/amlogic_start.S | 216 +++++++++
sys/arch/evbarm/amlogic/genassym.cf | 37 +
sys/arch/evbarm/amlogic/platform.h | 39 +
sys/arch/evbarm/conf/ODROID-C1 | 244 ++++++++++
sys/arch/evbarm/conf/ODROID-C1_INSTALL | 10 +
sys/arch/evbarm/conf/files.amlogic | 10 +
sys/arch/evbarm/conf/mk.amlogic | 33 +
sys/arch/evbarm/conf/std.amlogic | 26 +
40 files changed, 5283 insertions(+), 35 deletions(-)
diffs (truncated from 5783 to 300 lines):
diff -r 34cec44262b2 -r e3a301614f61 etc/etc.evbarm/Makefile.inc
--- a/etc/etc.evbarm/Makefile.inc Sat Mar 21 08:46:05 2015 +0000
+++ b/etc/etc.evbarm/Makefile.inc Sat Mar 21 08:51:17 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.63.2.3 2015/03/11 20:22:55 snj Exp $
+# $NetBSD: Makefile.inc,v 1.63.2.4 2015/03/21 08:51:17 snj Exp $
#
# etc.evbarm/Makefile.inc -- evbarm-specific etc Makefile targets
#
@@ -100,6 +100,8 @@
#EVBARM_BOARDS.armv7+= N900
EVBARM_BOARDS.armv7+= NETWALKER
EVBARM_BOARDS.armv7hf+= NETWALKER
+EVBARM_BOARDS.armv7+= ODROID-C1
+EVBARM_BOARDS.armv7hf+= ODROID-C1
EVBARM_BOARDS.armv7+= OMAP5EVM
EVBARM_BOARDS.armv7hf+= OMAP5EVM
#EVBARM_BOARDS.armv7+= OVERO
diff -r 34cec44262b2 -r e3a301614f61 sys/arch/arm/amlogic/amlogic_board.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/amlogic/amlogic_board.c Sat Mar 21 08:51:17 2015 +0000
@@ -0,0 +1,374 @@
+/* $NetBSD: amlogic_board.c,v 1.9.2.2 2015/03/21 08:51:17 snj Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_amlogic.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: amlogic_board.c,v 1.9.2.2 2015/03/21 08:51:17 snj Exp $");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <arm/bootconfig.h>
+#include <arm/cpufunc.h>
+
+#include <arm/amlogic/amlogic_reg.h>
+#include <arm/amlogic/amlogic_crureg.h>
+#include <arm/amlogic/amlogic_var.h>
+
+bus_space_handle_t amlogic_core_bsh;
+
+struct arm32_bus_dma_tag amlogic_dma_tag = {
+ _BUS_DMAMAP_FUNCS,
+ _BUS_DMAMEM_FUNCS,
+ _BUS_DMATAG_FUNCS,
+};
+
+#define CBUS_READ(x) \
+ bus_space_read_4(&amlogic_bs_tag, amlogic_core_bsh, \
+ AMLOGIC_CBUS_OFFSET + (x))
+#define CBUS_WRITE(x, v) \
+ bus_space_write_4(&amlogic_bs_tag, amlogic_core_bsh, \
+ AMLOGIC_CBUS_OFFSET + (x), (v))
+
+#define CBUS_SET_CLEAR(x, s, c) \
+ amlogic_reg_set_clear(&amlogic_bs_tag, amlogic_core_bsh, \
+ AMLOGIC_CBUS_OFFSET + (x), (s), (c))
+
+void
+amlogic_bootstrap(void)
+{
+ int error;
+
+ error = bus_space_map(&amlogic_bs_tag, AMLOGIC_CORE_BASE,
+ AMLOGIC_CORE_SIZE, 0, &amlogic_core_bsh);
+ if (error)
+ panic("%s: failed to map CORE registers: %d", __func__, error);
+
+ curcpu()->ci_data.cpu_cc_freq = amlogic_get_rate_a9();
+}
+
+uint32_t
+amlogic_get_rate_xtal(void)
+{
+ uint32_t ctlreg0;
+
+ ctlreg0 = CBUS_READ(PREG_CTLREG0_ADDR_REG);
+
+ return __SHIFTOUT(ctlreg0, PREG_CTLREG0_ADDR_CLKRATE) * 1000000;
+}
+
+uint32_t
+amlogic_get_rate_sys(void)
+{
+ uint32_t cntl;
+ uint64_t clk;
+ u_int mul, div, od;
+
+ clk = amlogic_get_rate_xtal();
+ cntl = CBUS_READ(HHI_SYS_PLL_CNTL_REG);
+ mul = __SHIFTOUT(cntl, HHI_SYS_PLL_CNTL_MUL);
+ div = __SHIFTOUT(cntl, HHI_SYS_PLL_CNTL_DIV);
+ od = __SHIFTOUT(cntl, HHI_SYS_PLL_CNTL_OD);
+
+ clk *= mul;
+ clk /= div;
+ clk >>= od;
+
+ return (uint32_t)clk;
+}
+
+uint32_t
+amlogic_get_rate_fixed(void)
+{
+ uint32_t cntl;
+ uint64_t clk;
+ u_int mul, div, od;
+
+ clk = amlogic_get_rate_xtal();
+ cntl = CBUS_READ(HHI_MPLL_CNTL_REG);
+ mul = __SHIFTOUT(cntl, HHI_MPLL_CNTL_MUL);
+ div = __SHIFTOUT(cntl, HHI_MPLL_CNTL_DIV);
+ od = __SHIFTOUT(cntl, HHI_MPLL_CNTL_OD);
+
+ clk *= mul;
+ clk /= div;
+ clk >>= od;
+
+ return (uint32_t)clk;
+}
+
+uint32_t
+amlogic_get_rate_a9(void)
+{
+ uint32_t cntl0, cntl1;
+ uint32_t rate = 0;
+
+ cntl0 = CBUS_READ(HHI_SYS_CPU_CLK_CNTL0_REG);
+ if (cntl0 & HHI_SYS_CPU_CLK_CNTL0_CLKSEL) {
+ switch (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_PLLSEL)) {
+ case 0:
+ rate = amlogic_get_rate_xtal();
+ break;
+ case 1:
+ rate = amlogic_get_rate_sys();
+ break;
+ case 2:
+ rate = 1250000000;
+ break;
+ }
+ } else {
+ rate = amlogic_get_rate_xtal();
+ }
+
+ KASSERTMSG(rate != 0, "couldn't determine A9 rate");
+
+ switch (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_SOUTSEL)) {
+ case 0:
+ break;
+ case 1:
+ rate /= 2;
+ break;
+ case 2:
+ rate /= 3;
+ break;
+ case 3:
+ cntl1 = CBUS_READ(HHI_SYS_CPU_CLK_CNTL1_REG);
+ rate /= (__SHIFTOUT(cntl1, HHI_SYS_CPU_CLK_CNTL1_SDIV) + 1);
+ break;
+ }
+
+ return rate;
+}
+
+uint32_t
+amlogic_get_rate_a9periph(void)
+{
+ const uint32_t cntl1 = CBUS_READ(HHI_SYS_CPU_CLK_CNTL1_REG);
+ const u_int div = __SHIFTOUT(cntl1,
+ HHI_SYS_CPU_CLK_CNTL1_PERIPH_CLK_MUX) + 2;
+
+ return amlogic_get_rate_a9() / div;
+}
+
+void
+amlogic_eth_init(void)
+{
+ CBUS_WRITE(EE_CLK_GATING1_REG,
+ CBUS_READ(EE_CLK_GATING1_REG) | EE_CLK_GATING1_ETHERNET);
+}
+
+void
+amlogic_rng_init(void)
+{
+ CBUS_WRITE(EE_CLK_GATING0_REG,
+ CBUS_READ(EE_CLK_GATING0_REG) | EE_CLK_GATING0_RNG);
+ CBUS_WRITE(EE_CLK_GATING3_REG,
+ CBUS_READ(EE_CLK_GATING3_REG) | EE_CLK_GATING3_RNG);
+}
+
+void
+amlogic_sdhc_init(void)
+{
+ /* enable SDHC clk */
+ CBUS_WRITE(EE_CLK_GATING0_REG,
+ CBUS_READ(EE_CLK_GATING0_REG) | EE_CLK_GATING0_SDHC);
+}
+
+int
+amlogic_sdhc_select_port(int port)
+{
+ switch (port) {
+ case AMLOGIC_SDHC_PORT_B:
+ /* CARD -> SDHC pin mux settings */
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_5_REG, 0, 0x00007c00);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0, 0x7c000000);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x0000fc00);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_8_REG, 0, 0x00000600);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0x000000f0, 0);
+ break;
+ case AMLOGIC_SDHC_PORT_C:
+ /* BOOT -> SDHC pin mux settings */
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_2_REG, 0, 0x04c000f0);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_5_REG, 0, 0x00007c00);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_6_REG, 0, 0xff000000);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_4_REG, 0x70000000, 0);
+ CBUS_SET_CLEAR(PERIPHS_PIN_MUX_7_REG, 0x000c0000, 0);
+ break;
+ default:
+ return EINVAL;
+ }
+
+ return 0;
+}
+
+static void
+amlogic_usbphy_clkgate_enable(int port)
+{
+ switch (port) {
+ case 0:
+ CBUS_WRITE(EE_CLK_GATING1_REG,
+ CBUS_READ(EE_CLK_GATING1_REG) |
+ EE_CLK_GATING1_USB_GENERAL |
+ EE_CLK_GATING1_USB0);
+ CBUS_WRITE(EE_CLK_GATING2_REG,
+ CBUS_READ(EE_CLK_GATING2_REG) |
+ EE_CLK_GATING2_USB0_TO_DDR);
+ break;
+ case 1:
+ CBUS_WRITE(EE_CLK_GATING1_REG,
+ CBUS_READ(EE_CLK_GATING1_REG) |
+ EE_CLK_GATING1_USB_GENERAL |
+ EE_CLK_GATING1_USB1);
+ CBUS_WRITE(EE_CLK_GATING2_REG,
+ CBUS_READ(EE_CLK_GATING2_REG) |
+ EE_CLK_GATING2_USB1_TO_DDR);
+ break;
+ }
+}
+
+void
+amlogic_usbphy_init(int port)
+{
+ bus_space_tag_t bst = &amlogic_bs_tag;
+ bus_space_handle_t bsh = amlogic_core_bsh;
+ bus_size_t ctrl_reg, cfg_reg, adp_bc_reg, gpioao_reg;
+ uint32_t ctrl, cfg, adp_bc, gpioao;
+ u_int pin, pol;
+ bool gpio_power = false, gpio_reset = false, aca_enable = false;
+
+ gpioao_reg = AMLOGIC_GPIOAO_OFFSET;
+
+ switch (port) {
+ case 0:
+ cfg_reg = PREI_USB_PHY_A_CFG_REG;
+ ctrl_reg = PREI_USB_PHY_A_CTRL_REG;
+ adp_bc_reg = PREI_USB_PHY_A_ADP_BC_REG;
+ pin = 5;
+ pol = 1;
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