[src/trunk]: src/sys/arch/emips/emips Fix a longstanding "freeze right after ...

[tsutsui <tsutsui%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/619992b612a4
branches:  trunk
changeset: 847127:619992b612a4
user:      tsutsui <tsutsui%NetBSD.org@localhost>
date:      Wed Dec 11 16:16:13 2019 +0000

description:
Fix a longstanding "freeze right after enabling interrupt" problem.

With this fix, finally NetBSD/emips on Giano is fully functional.
See PR/45080 for more details.

Should be pulled up to netbsd-9.

diffstat:

 sys/arch/emips/emips/interrupt.c |  25 +++++++++++++++++++++++--
 1 files changed, 23 insertions(+), 2 deletions(-)

diffs (53 lines):

diff -r 5765176c2d43 -r 619992b612a4 sys/arch/emips/emips/interrupt.c
--- a/sys/arch/emips/emips/interrupt.c  Wed Dec 11 15:08:45 2019 +0000
+++ b/sys/arch/emips/emips/interrupt.c  Wed Dec 11 16:16:13 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: interrupt.c,v 1.7 2019/12/09 16:19:11 tsutsui Exp $    */
+/*     $NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $    */
 
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.7 2019/12/09 16:19:11 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2019/12/11 16:16:13 tsutsui Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -102,6 +102,19 @@
 
        curcpu()->ci_data.cpu_nintr++;
 
+#if 0
+       /*
+        * According to Giano simulator sources (Cpus/mips_cpu.cpp),
+        * interrupt register bits in CAUSE register are updated
+        * only when the exception is triggered. This means checking
+        * CAUSE register via splintr() in a while loop in this
+        * interrupt handler doesn't work as expected on Giano.
+        *
+        * I don't know whether the real FPGA eMIPS has the same
+        * design as the Giano simulator, but for now I'd like to
+        * choose 'call only one handler per each interrupt' strategy,
+        * as the original NetBSD/emips implementation.
+        */
        while (ppl < (ipl = splintr(&ipending))) {
                splx(ipl);
                /* device interrupts */
@@ -110,6 +123,14 @@
                }
                (void)splhigh();
        }
+#else
+       ipl = splintr(&ipending);
+       __USE(ipl);
+       /* device interrupts */
+       if (ipending & MIPS_INT_MASK_5) {
+               (*platform.iointr)(status, pc, ipending);
+       }
+#endif
 }
 
 /*