[src/trunk]: src/sys/arch/evbmips/ingenic use #ifdef USE_OST to switch betwee...

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/57c0c26b926c
branches:  trunk
changeset: 805255:57c0c26b926c
user:      macallan <macallan%NetBSD.org@localhost>
date:      Fri Dec 26 17:43:32 2014 +0000

description:
use #ifdef USE_OST to switch between OS Timer and timer 5
always enable interrupts, not just with INGENIC_CLOCK_DEBUG

diffstat:

 sys/arch/evbmips/ingenic/clock.c |  19 +++++++++++++------
 1 files changed, 13 insertions(+), 6 deletions(-)

diffs (78 lines):

diff -r 28c2426ac9d8 -r 57c0c26b926c sys/arch/evbmips/ingenic/clock.c
--- a/sys/arch/evbmips/ingenic/clock.c  Fri Dec 26 16:53:33 2014 +0000
+++ b/sys/arch/evbmips/ingenic/clock.c  Fri Dec 26 17:43:32 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $ */
+/*     $NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.3 2014/12/23 15:07:33 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.4 2014/12/26 17:43:32 macallan Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -75,8 +75,8 @@
        /* start the timer interrupt */
        cnt = readreg(JZ_OST_CNT_LO);
        ci->ci_next_cp0_clk_intr = cnt + ci->ci_cycles_per_hz;
+       writereg(JZ_TC_TFCR, TFR_OSTFLAG);
        writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
-       writereg(JZ_TC_TFCR, TFR_OSTFLAG);
        /*
         * XXX
         * We can use OST or one of the regular timers to generate the 100hz
@@ -93,7 +93,7 @@
         * For now, use OST and hope we'll figure out how to make it fire on
         * INT2.
         */
-#if 1
+#ifdef USE_OST
        writereg(JZ_TC_TMCR, TFR_OSTFLAG);
 #else
        writereg(JZ_TC_TECR, TESR_TCST5);       /* disable timer 5 */
@@ -108,8 +108,9 @@
 
 #ifdef INGENIC_CLOCK_DEBUG
        printf("INTC %08x %08x\n", readreg(JZ_ICSR0), readreg(JZ_ICSR1));
+       printf("ICMR0 %08x\n", readreg(JZ_ICMR0));
+#endif
        writereg(JZ_ICMCR0, 0x0c000000); /* TCU2, OST */
-#endif
        spl0();
 #ifdef INGENIC_CLOCK_DEBUG
        printf("TFR: %08x\n", readreg(JZ_TC_TFR));
@@ -191,8 +192,9 @@
 ingenic_clockintr(uint32_t id)
 {
        struct cpu_info * const ci = curcpu();
+#ifdef USE_OST
        uint32_t new_cnt;
-
+#endif
        ci->ci_ev_count_compare.ev_count++;
 
        /* clear flags */
@@ -200,6 +202,7 @@
 
        KASSERT((ci->ci_cycles_per_hz & ~(0xffffffff)) == 0);
        ci->ci_next_cp0_clk_intr += (uint32_t)(ci->ci_cycles_per_hz & 0xffffffff);
+#ifdef USE_OST
        writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
 
        /* Check for lost clock interrupts */
@@ -215,6 +218,10 @@
                writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
                curcpu()->ci_ev_count_compare_missed.ev_count++;
        }
+       writereg(JZ_TC_TFCR, TFR_OSTFLAG);
+#else
+       writereg(JZ_TC_TFCR, TFR_FFLAG5);
+#endif
 
 #ifdef INGENIC_CLOCK_DEBUG
        cnt++;