Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/ia64/ia64 Updates from FreeBSD, mostly compile-tested
details: https://anonhg.NetBSD.org/src/rev/e20911830ae4
branches: trunk
changeset: 822807:e20911830ae4
user: scole <scole%NetBSD.org@localhost>
date: Sat Apr 08 17:42:47 2017 +0000
description:
Updates from FreeBSD, mostly compile-tested
diffstat:
sys/arch/ia64/ia64/exception.S | 757 ++++++++++++++++++++++++++++------------
1 files changed, 535 insertions(+), 222 deletions(-)
diffs (truncated from 1220 to 300 lines):
diff -r b02d9ff75088 -r e20911830ae4 sys/arch/ia64/ia64/exception.S
--- a/sys/arch/ia64/ia64/exception.S Sat Apr 08 17:40:50 2017 +0000
+++ b/sys/arch/ia64/ia64/exception.S Sat Apr 08 17:42:47 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: exception.S,v 1.5 2011/10/01 15:59:27 chs Exp $ */
+/* $NetBSD: exception.S,v 1.6 2017/04/08 17:42:47 scole Exp $ */
/*-
* Copyright (c) 2003,2004 Marcel Moolenaar
@@ -28,18 +28,206 @@
*/
#include <machine/asm.h>
-#include <machine/pte.h>
+/* __FBSDID("$FreeBSD: releng/10.1/sys/ia64/ia64/exception.S 268200 2014-07-02 23:47:43Z marcel $"); */
#include "assym.h"
/*
+ * Nested TLB restart tokens. These are used by the
+ * nested TLB handler for jumping back to the code
+ * where the nested TLB was caused.
+ */
+#define NTLBRT_SAVE 0x12c12c
+#define NTLBRT_RESTORE 0x12c12d
+
+/*
* ar.k7 = kernel memory stack
* ar.k6 = kernel register stack
* ar.k5 = EPC gateway page
* ar.k4 = PCPU data
*/
- .text
+ .section .ivt.data, "aw"
+
+ .align 8
+ .global ia64_kptdir
+ .size ia64_kptdir, 8
+ia64_kptdir: data8 0
+
+
+#ifdef XTRACE
+
+ .align 8
+ .global ia64_xtrace_mask
+ .size ia64_xtrace_mask, 8
+ia64_xtrace_mask: data8 0
+
+ .align 4
+ .global ia64_xtrace_enabled
+ .size ia64_xtrace_enabled, 4
+ia64_xtrace_enabled: data4 0
+
+#define XTRACE_HOOK(offset) \
+{ .mii ; \
+ nop 0 ; \
+ mov r31 = b7 ; \
+ mov r28 = pr ; \
+} ; \
+{ .mib ; \
+ nop 0 ; \
+ mov r25 = ip ; \
+ br.sptk ia64_xtrace_write ;; \
+} ; \
+{ .mii ; \
+ nop 0 ; \
+ mov b7 = r31 ; \
+ mov pr = r28, 0x1ffff ;; \
+}
+
+ .section .ivt.text, "ax"
+
+// We can only use r25, r26 & r27
+ENTRY_NOPROFILE(ia64_xtrace_write, 0)
+{ .mlx
+ add r25 = 16, r25
+ movl r26 = ia64_xtrace_enabled
+ ;;
+}
+{ .mmi
+ mov r27 = ar.k3
+ ld4 r26 = [r26]
+ mov b7 = r25
+ ;;
+}
+{ .mib
+ add r25 = -32, r25
+ cmp.eq p15,p0 = r0, r26
+(p15) br.dptk.few b7
+ ;;
+}
+{ .mib
+ nop 0
+ cmp.eq p15,p0 = r0, r27
+(p15) br.dptk.few b7
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x00 IVT
+ mov r26 = ar.itc
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r26, 8 // 0x08 ITC
+ mov r25 = cr.iip
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x10 IIP
+ mov r26 = cr.ifa
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r26, 8 // 0x18 IFA
+ mov r25 = cr.isr
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x20 ISR
+ mov r26 = cr.ipsr
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r26, 8 // 0x28 IPSR
+ mov r25 = cr.itir
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x30 ITIR
+ mov r26 = cr.iipa
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r26, 8 // 0x38 IIPA
+ mov r25 = cr.ifs
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x40 IFS
+ mov r26 = cr.iim
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r26, 8 // 0x48 IIM
+ mov r25 = cr.iha
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x50 IHA
+ mov r26 = ar.unat
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r26, 8 // 0x58 UNAT
+ mov r25 = ar.rsc
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x60 RSC
+ mov r26 = ar.bsp
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r26, 8 // 0x68 BSP
+ mov r25 = r13
+ nop 0
+ ;;
+}
+{ .mmi
+ st8 [r27] = r25, 8 // 0x70 PCPU/TLS
+ mov r26 = r12
+ nop 0
+ ;;
+}
+{ .mlx
+ st8 [r27] = r26, 8 // 0x78 SP
+ movl r25 = ia64_xtrace_mask
+ ;;
+}
+{ .mmi
+ ld8 r26 = [r25]
+ ;;
+ and r25 = r27, r26
+ nop 0
+ ;;
+}
+{ .mib
+ mov ar.k3 = r25
+ nop 0
+ br.sptk b7
+ ;;
+}
+END(ia64_xtrace_write)
+
+#else /* XTRACE */
+
+#define XTRACE_HOOK(offset)
+
+ .section .ivt.text, "ax"
+
+#endif /* XTRACE */
/*
* exception_save: save interrupted state
@@ -67,7 +255,7 @@
;;
}
{ .mmi
- cmp.le p14,p15=5,r31
+ cmp.le p14,p15=IA64_VM_MINKERN_REGION,r31
;;
(p15) mov r23=ar.k7 // kernel memory stack
(p14) mov r23=sp
@@ -82,42 +270,57 @@
}
{ .mmi
mov ar.rsc=0
- sub r19=r23,r30
- add r31=8,r30
- ;;
-}
-{ .mlx
mov r22=cr.iip
- movl r26=exception_save_restart
+ addl r29=NTLBRT_SAVE,r0 // 22-bit restart token.
;;
}
/*
- * We have a 1KB aligned trapframe, pointed to by sp. If we write
- * to the trapframe, we may trigger a data nested TLB fault. By
- * aligning the trapframe on a 1KB boundary, we guarantee that if
- * we get a data nested TLB fault, it will be on the very first
- * write. Since the data nested TLB fault does not preserve any
- * state, we have to be careful what we clobber. Consequently, we
- * have to be careful what we use here. Below a list of registers
- * that are currently alive:
+ * We have a 1KB aligned trapframe, pointed to by r30. We can't
+ * reliably write to the trapframe using virtual addressing, due
+ * to the fact that TC entries we depend on can be removed by:
+ * 1. ptc.g instructions issued by other threads/cores/CPUs, or
+ * 2. TC modifications in another thread on the same core.
+ * When our TC entry gets removed, we get nested TLB faults and
+ * since no state is saved, we can only deal with those when
+ * explicitly coded and expected.
+ * As such, we switch to physical addressing and account for the
+ * fact that the tpa instruction can cause a nested TLB fault.
+ * Since the data nested TLB fault does not preserve any state,
+ * we have to be careful what we clobber. Consequently, we have
+ * to be careful what we use here. Below a list of registers that
+ * are considered alive:
* r16,r17=arguments
* r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS
- * r26=restart point
- * r30,r31=trapframe pointers
+ * r29=restart token
+ * r30=trapframe pointers
* p14,p15=memory stack switch
*/
exception_save_restart:
+ tpa r24=r30 // Nested TLB fault possible
+ sub r19=r23,r30
+ nop 0
+ ;;
+
+ rsm psr.dt
+ add r29=16,r19 // Clobber restart token
+ mov r30=r24
+ ;;
+ srlz.d
+ add r31=8,r24
+ ;;
+
+ // r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS
+ // r29=delta
{ .mmi
st8 [r30]=r19,16 // length
st8 [r31]=r0,16 // flags
- add r19=16,r19
;;
}
{ .mmi
st8.spill [r30]=sp,16 // sp
st8 [r31]=r20,16 // unat
- sub sp=r23,r19
+ sub sp=r23,r29
Home |
Main Index |
Thread Index |
Old Index