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[src/trunk]: src/sys/arch/arm/samsung EXYNOS Rewrite step 2 of N: New exynos_...
details: https://anonhg.NetBSD.org/src/rev/d5bc72ba1315
branches: trunk
changeset: 812318:d5bc72ba1315
user: marty <marty%NetBSD.org@localhost>
date: Fri Dec 11 04:03:44 2015 +0000
description:
EXYNOS Rewrite step 2 of N: New exynos_gpio.c
I can't bring myself to fully nuke from orbit, so there are really two
things in this checkin:
1) A major rewrite of exynos_gpio.c, based mostly on the Nvidia
tegra_gpio.c file. This is missing a major function that will be
added the first time a customer for it is integrated, which is meant to
select pins based on aliases, rather than pin bank names.
2) A small number of changes to other files that keep the tree compiling
and progressing as far as ever; except it is now 5422 specific and
will not boot on the other exynos socs, which I don't have hardware to
test.
The choice to remove functionality is always controversial, but since
we are doing a significant rewrite and I don't have either
documentation or hardware *and* none of the code really works now
anyway, I'm taking the stance that only tested functionality should be
added, and that we'll layer the other exynos socs on this once it
fully boots.
diffstat:
sys/arch/arm/samsung/exynos5_reg.h | 15 +-
sys/arch/arm/samsung/exynos_gpio.c | 930 +++++++++---------------------------
sys/arch/arm/samsung/exynos_i2c.c | 11 +-
sys/arch/arm/samsung/exynos_soc.c | 88 +---
sys/arch/arm/samsung/exynos_var.h | 4 +-
sys/arch/arm/samsung/mct.c | 26 +-
6 files changed, 265 insertions(+), 809 deletions(-)
diffs (truncated from 1450 to 300 lines):
diff -r b111ed96ac83 -r d5bc72ba1315 sys/arch/arm/samsung/exynos5_reg.h
--- a/sys/arch/arm/samsung/exynos5_reg.h Fri Dec 11 03:55:18 2015 +0000
+++ b/sys/arch/arm/samsung/exynos5_reg.h Fri Dec 11 04:03:44 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos5_reg.h,v 1.20 2014/12/29 22:58:59 skrll Exp $ */
+/* $NetBSD: exynos5_reg.h,v 1.21 2015/12/11 04:03:44 marty Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -51,6 +51,13 @@
* 0x40000000 0xFFFFFFFF DRAM
*/
+/* MJF: The GPIO offset names made no sense and the values wer wrong. */
+#define EXYNOS5_GPIO_MUXA_OFFSET 0x03400000
+#define EXYNOS5_GPIO_MUXB_OFFSET 0x03410000
+#define EXYNOS5_GPIO_MUXC_OFFSET 0x04000000
+#define EXYNOS5_GPIO_MUXD_OFFSET 0x04010000
+#define EXYNOS5_GPIO_MUXE_OFFSET 0x03860000
+
/* CORE */
#define EXYNOS5_CORE_SIZE 0x0f000000
#define EXYNOS5_SDRAM_PBASE 0x40000000
@@ -103,7 +110,7 @@
#define EXYNOS5_AS_A_LEFT_BUS_OFFSET 0x00CE0000
#define EXYNOS5_AS_A_RIGHT0_BUS_OFFSET 0x00CF0000
#define EXYNOS5_AS_A_DISP1_BUS_OFFSET 0x00D00000
-#define EXYNOS5_GPIO_C2C_OFFSET 0x00D10000
+/*#define EXYNOS5_GPIO_C2C_OFFSET 0x00D10000*/
#define EXYNOS5_DREXII_OFFSET 0x00DD0000
#define EXYNOS5_AS_A_EFCON_OFFSET 0x00DE0000
#define EXYNOS5_AP_C2C_OFFSET 0x00E00000
@@ -117,7 +124,7 @@
#define EXYNOS5_MFC_OFFSET 0x01000000
#define EXYNOS5_SYSMMU_MFC0_R 0x01200000
#define EXYNOS5_SYSMMU_MFC1_L 0x01210000
-#define EXYNOS5_GPIO_LEFT_OFFSET 0x01400000
+/*#define EXYNOS5_GPIO_LEFT_OFFSET 0x04010000*/
#define EXYNOS5_AS_A_MFC_OFFSET 0x01680000
#define EXYNOS5_AS_A_GENX_OFFSET 0x016A0000
#define EXYNOS5_3D ENGINE_OFFSET 0x01800000
@@ -236,7 +243,7 @@
#define EXYNOS5_SYSMMU_FIMC_DIS0 0x032D0000
#define EXYNOS5_SYSMMU_FIMC_DIS1 0x032E0000
#define EXYNOS5_SYSMMU_FIMC_3DNR_OFFSET 0x032F0000
-#define EXYNOS5_GPIO_RIGHT_OFFSET 0x03400000
+/*#define EXYNOS5_GPIO_RIGHT_OFFSET 0x04000000*/
#define EXYNOS5_AS_A_MFC0_OFFSET 0x03620000
#define EXYNOS5_AS_A_ISP0_OFFSET 0x03640000
#define EXYNOS5_AS_A_ISP1_OFFSET 0x03650000
diff -r b111ed96ac83 -r d5bc72ba1315 sys/arch/arm/samsung/exynos_gpio.c
--- a/sys/arch/arm/samsung/exynos_gpio.c Fri Dec 11 03:55:18 2015 +0000
+++ b/sys/arch/arm/samsung/exynos_gpio.c Fri Dec 11 04:03:44 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_gpio.c,v 1.12 2014/12/29 22:34:08 skrll Exp $ */
+/* $NetBSD: exynos_gpio.c,v 1.13 2015/12/11 04:03:44 marty Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include "gpio.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.12 2014/12/29 22:34:08 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.13 2015/12/11 04:03:44 marty Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -42,21 +42,14 @@
#include <sys/intr.h>
#include <sys/systm.h>
#include <sys/kmem.h>
+#include <sys/gpio.h>
+
+#include <dev/gpio/gpiovar.h>
#include <arm/samsung/exynos_reg.h>
#include <arm/samsung/exynos_io.h>
#include <arm/samsung/exynos_intr.h>
-#include <sys/gpio.h>
-#include <dev/gpio/gpiovar.h>
-
-static int exynos_gpio_match(device_t, cfdata_t, void *);
-static void exynos_gpio_attach(device_t, device_t, void *);
-
-static int exynos_gpio_pin_read(void *, int);
-static void exynos_gpio_pin_write(void *, int, int);
-static void exynos_gpio_pin_ctl(void *, int, int);
-
struct exynos_gpio_pin_cfg {
uint32_t cfg;
uint32_t pud;
@@ -65,277 +58,108 @@
uint32_t pudpwd;
};
-struct exynos_gpio_pin_group {
- const char grp_name[6];
- const bus_addr_t grp_core_offset;
- const uint8_t grp_bits;
-
- uint8_t grp_pin_mask;
- uint8_t grp_pin_inuse_mask;
- bus_space_handle_t grp_bsh;
- struct exynos_gpio_pin_cfg grp_cfg;
- struct gpio_chipset_tag grp_gc_tag;
-};
-
-
-#define GPIO_REG(v,s,o) (EXYNOS##v##_GPIO_##s##_OFFSET + (o))
-#define GPIO_GRP(v, s, o, n, b) \
- { \
- .grp_name = #n, \
- .grp_core_offset = GPIO_REG(v,s,o), \
- .grp_bits = b,\
- }
+struct exynos_gpio_softc;
-#ifdef EXYNOS4
-/*
- * Exynos 4412 contains 304 multi-functional input/output port pins and 164
- * memory port pins. There are 37 general port groups and two memory port
- * groups. They are:
- *
- * GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow
- * control, and/or 2xI2C
- *
- * GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM
- *
- * GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C,
- * and/or SPI
- *
- * GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI
- *
- * GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F,
- * HSI, and/ or Trace I/F
- *
- * GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F
- *
- * GPJ0, GPJ1: 13 in/out ports-CAM I/F
- *
- * GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC
- * (8-bit MMC)), and/or GPS debugging I/F
- *
- * GPL0, GPL1: 11 in/out ports-GPS I/F
- *
- * GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F
- *
- * GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad
- * I/F
- *
- * GPZ: 7 in/out ports-low Power I2S and/or PCM
- *
- * GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One
- * NAND)
- *
- * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information
- * about EBI configuration, refer to Chapter 5, and 6)
- *
- * MP1_0-MP1_9: 78 DRAM1 ports. NOTE: GPIO registers does not control these
- * ports.
- *
- * MP2_0-MP2_9: 78 DRAM2 ports. NOTE: GPIO registers does not control these
- * ports.
- *
- * ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK
- *
- * ETC7, ETC8 : 4 clock port for C2C
- *
- */
-
-static struct exynos_gpio_pin_group exynos4_pin_groups[] = {
- GPIO_GRP(4, LEFT, 0x0000, GPA0, 8),
- GPIO_GRP(4, LEFT, 0x0020, GPA1, 6),
- GPIO_GRP(4, LEFT, 0x0040, GPB, 8),
- GPIO_GRP(4, LEFT, 0x0060, GPC0, 5),
- GPIO_GRP(4, LEFT, 0x0080, GPC1, 5),
- GPIO_GRP(4, LEFT, 0x00A0, GPD0, 4),
- GPIO_GRP(4, LEFT, 0x00C0, GPD1, 4),
- GPIO_GRP(4, LEFT, 0x0180, GPF0, 8),
- GPIO_GRP(4, LEFT, 0x01A0, GPF1, 8),
- GPIO_GRP(4, LEFT, 0x01C0, GPF2, 8),
- GPIO_GRP(4, LEFT, 0x01E0, GPF3, 8),
- GPIO_GRP(4, LEFT, 0x0240, GPJ0, 8),
- GPIO_GRP(4, LEFT, 0x0260, GPJ1, 5),
- /* EXTINT skipped */
-
- GPIO_GRP(4, RIGHT, 0x0040, GPK0, 8),
- GPIO_GRP(4, RIGHT, 0x0060, GPK1, 8),
- GPIO_GRP(4, RIGHT, 0x0080, GPK2, 7),
- GPIO_GRP(4, RIGHT, 0x00A0, GPK3, 7),
- GPIO_GRP(4, RIGHT, 0x00C0, GPL0, 7),
- GPIO_GRP(4, RIGHT, 0x00E0, GPL1, 2),
- GPIO_GRP(4, RIGHT, 0x0100, GPL2, 8),
- GPIO_GRP(4, RIGHT, 0x0120, GPY0, 6),
- GPIO_GRP(4, RIGHT, 0x0140, GPY1, 4),
- GPIO_GRP(4, RIGHT, 0x0160, GPY2, 6),
- GPIO_GRP(4, RIGHT, 0x0180, GPY3, 8),
- GPIO_GRP(4, RIGHT, 0x01A0, GPY4, 8),
- GPIO_GRP(4, RIGHT, 0x01C0, GPY5, 8),
- GPIO_GRP(4, RIGHT, 0x01E0, GPY6, 8),
- GPIO_GRP(4, RIGHT, 0x0200, ETC0, 6),
- GPIO_GRP(4, RIGHT, 0x0220, ETC6, 8),
- GPIO_GRP(4, RIGHT, 0x0260, GPM0, 8),
- GPIO_GRP(4, RIGHT, 0x0280, GPM1, 7),
- GPIO_GRP(4, RIGHT, 0x02A0, GPM2, 5),
- GPIO_GRP(4, RIGHT, 0x02C0, GPM3, 8),
- GPIO_GRP(4, RIGHT, 0x02E0, GPM4, 8),
- /* EXTINT skipped */
- GPIO_GRP(4, RIGHT, 0x0C00, GPX0, 8),
- GPIO_GRP(4, RIGHT, 0x0C20, GPX1, 8),
- GPIO_GRP(4, RIGHT, 0x0C40, GPX2, 8),
- GPIO_GRP(4, RIGHT, 0x0C60, GPX3, 8),
- /* EXTINT skipped */
-
- GPIO_GRP(4, I2S0, 0x0000, GPZ, 8),
- /* EXTINT skipped */
+struct exynos_gpio_bank {
+ const char bank_name[6];
+ struct exynos_gpio_softc *bank_sc;
+ device_t bank_dev;
+ struct gpio_chipset_tag bank_gc;
+ gpio_pin_t bank_pins[8];
- GPIO_GRP(4, C2C, 0x0000, GPV0, 8),
- GPIO_GRP(4, C2C, 0x0020, GPV1, 8),
- GPIO_GRP(4, C2C, 0x0040, ETC7, 2),
- GPIO_GRP(4, C2C, 0x0060, GPV2, 8),
- GPIO_GRP(4, C2C, 0x0080, GPV3, 8),
- GPIO_GRP(4, C2C, 0x00A0, ETC8, 2),
- GPIO_GRP(4, C2C, 0x00C0, GPV4, 2),
- /* EXTINT skipped */
-};
-#endif
-
-
-#ifdef EXYNOS5
-
-/*
- * Exynos 5250 contains 253 multi-functional input/output port pins and 160
- * memory port pins. There are 39 general port groups and 2 memory port
- * groups. They are:
- *
- * GPA0, GPA1: 14 in/out ports-2xUART with flow control, UART without flow
- * control, and/or 2xI2C , and/or2xHS-I2C
- *
- * GPA2: 8 in/out ports-2xSPI, and/or I2C
- *
- * GPB0, GPB1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C,
- * and/or SPI
- *
- * GPB2, GPB3: 8 in/out ports-PWM, I2C, and/or I2C ,and/or HS-I2C
- *
- * GPC0, GPC1: 11 in/out ports-1xMMC (8-bit MMC) I/F
- *
- * GPC2: 7 in/out ports-1xMMC (4-bit MMC) I/F
- *
- * GPC3, GPC4: 14 in/out ports-2xMMC (4-bit MMC) and/or 1xMMC (8-bit MMC) I/F
- *
- * GPD0: 4 pin/out ports-1xUART with flow control I/F
- *
- * GPD1: 8 pin/out ports-HSI I/F
- *
- * GPE0, GPE1, GPF0, GPF1, GPG0, GPG1, GPG2, GPH0, GPH1: 48 in/out ports-CAM
- * I/F, and/or Trace I/F
- *
- * GPV0, GPV1, GPV2, GPV3, GPV4: 34 in/out ports-C2C I/F
- *
- * GPX0, 1, 2, 3: 32 in/out port-external wake-up interrupts (up-to 32-bit),
- * and/or AUD I/F, and/or MFC I/F (GPX groups are in alive region)
- *
- * GPY0, GPY1, GPY2: 16 in/out ports-control signals of EBI (SROM)
- *
- * GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI
- *
- * GPZ: 7 in/out ports-low power I2S and/or PCM
- *
- * MP1_0-MP1_10: 80 DRAM1 ports NOTE: GPIO registers do not control these
- * ports.
- *
- * MP2_0-MP2_10: 80 DRAM2 ports NOTE: GPIO registers do not control these
- * ports.
- *
- * ETC0, ETC5, ETC6, ETC7, ETC8: 22 in/out ETC ports-JTAG, C2C_CLK (Rx),
- * RESET, CLOCK, USBOTG and USB3, C2C_CLK (Tx)
- */
+ const bus_addr_t bank_core_offset;
+ const uint8_t bank_bits;
-static struct exynos_gpio_pin_group exynos5_pin_groups[] = {
- GPIO_GRP(5, LEFT, 0x0000, GPA0, 8),
- GPIO_GRP(5, LEFT, 0x0020, GPA1, 6),
- GPIO_GRP(5, LEFT, 0x0040, GPA2, 8),
- GPIO_GRP(5, LEFT, 0x0060, GPB0, 5),
- GPIO_GRP(5, LEFT, 0x0080, GPB1, 5),
- GPIO_GRP(5, LEFT, 0x00A0, GPB2, 4),
- GPIO_GRP(5, LEFT, 0x00C0, GPB3, 4),
- GPIO_GRP(5, LEFT, 0x00E0, GPC0, 7),
- GPIO_GRP(5, LEFT, 0x0100, GPC1, 4),
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