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[src/trunk]: src/external/bsd/llvm/dist Mark files not tagged with r319952 as...
details: https://anonhg.NetBSD.org/src/rev/f3f851846949
branches: trunk
changeset: 828517:f3f851846949
user: joerg <joerg%NetBSD.org@localhost>
date: Sun Dec 17 21:28:52 2017 +0000
description:
Mark files not tagged with r319952 as dead.
diffstat:
external/bsd/llvm/dist/clang/bindings/python/tests/test_exception_specification_kind.py | 27 -
external/bsd/llvm/dist/clang/test/CodeGen/mips-aggregate-arg.c | 38 -
external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/thread-pointer.ll | 60 -
external/bsd/llvm/dist/llvm/test/CodeGen/X86/f16c-schedule.ll | 144 --
external/bsd/llvm/dist/llvm/test/CodeGen/X86/lea32-schedule.ll | 653 ----------
external/bsd/llvm/dist/llvm/test/CodeGen/X86/lea64-schedule.ll | 534 --------
external/bsd/llvm/dist/llvm/test/CodeGen/X86/popcnt-schedule.ll | 167 --
7 files changed, 0 insertions(+), 1623 deletions(-)
diffs (truncated from 1651 to 300 lines):
diff -r b5eb87bce03c -r f3f851846949 external/bsd/llvm/dist/clang/bindings/python/tests/test_exception_specification_kind.py
--- a/external/bsd/llvm/dist/clang/bindings/python/tests/test_exception_specification_kind.py Sun Dec 17 21:16:57 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,27 +0,0 @@
-import clang.cindex
-from clang.cindex import ExceptionSpecificationKind
-from .util import get_tu
-
-
-def find_function_declarations(node, declarations=[]):
- if node.kind == clang.cindex.CursorKind.FUNCTION_DECL:
- declarations.append((node.spelling, node.exception_specification_kind))
- for child in node.get_children():
- declarations = find_function_declarations(child, declarations)
- return declarations
-
-
-def test_exception_specification_kind():
- source = """int square1(int x);
- int square2(int x) noexcept;
- int square3(int x) noexcept(noexcept(x * x));"""
-
- tu = get_tu(source, lang='cpp', flags=['-std=c++14'])
-
- declarations = find_function_declarations(tu.cursor)
- expected = [
- ('square1', ExceptionSpecificationKind.NONE),
- ('square2', ExceptionSpecificationKind.BASIC_NOEXCEPT),
- ('square3', ExceptionSpecificationKind.COMPUTED_NOEXCEPT)
- ]
- assert declarations == expected
diff -r b5eb87bce03c -r f3f851846949 external/bsd/llvm/dist/clang/test/CodeGen/mips-aggregate-arg.c
--- a/external/bsd/llvm/dist/clang/test/CodeGen/mips-aggregate-arg.c Sun Dec 17 21:16:57 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n32 | FileCheck -check-prefix=N32-N64 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s -target-abi n64 | FileCheck -check-prefix=N32-N64 %s
-
-struct t1 {
- char t1[10];
-};
-
-struct t2 {
- char t2[20];
-};
-
-struct t3 {
- char t3[65];
-};
-
-extern struct t1 g1;
-extern struct t2 g2;
-extern struct t3 g3;
-extern void f1(struct t1);
-extern void f2(struct t2);
-extern void f3(struct t3);
-
-void f() {
-
-// O32: call void @f1(i32 inreg %{{[0-9]+}}, i32 inreg %{{[0-9]+}}, i16 inreg %{{[0-9]+}})
-// O32: call void @f2(%struct.t2* byval align 4 %{{.*}})
-// O32: call void @f3(%struct.t3* byval align 4 %{{.*}})
-
-// N32-N64: call void @f1(i64 inreg %{{[0-9]+}}, i16 inreg %{{[0-9]+}})
-// N32-N64: call void @f2(i64 inreg %{{[0-9]+}}, i64 inreg %{{[0-9]+}}, i32 inreg %{{[0-9]+}})
-// N32-N64: call void @f3(%struct.t3* byval align 8 %{{.*}})
-
- f1(g1);
- f2(g2);
- f3(g3);
-}
-
diff -r b5eb87bce03c -r f3f851846949 external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/thread-pointer.ll
--- a/external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/thread-pointer.ll Sun Dec 17 21:16:57 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
-
-@x = thread_local local_unnamed_addr global i32 0, align 4
-@y = thread_local local_unnamed_addr global i32 0, align 4
-
-; Machine LICM should hoist the mrs into the loop preheader.
-; CHECK-LABEL: @test1
-; CHECK: BB#1:
-; CHECK: mrs x[[BASE:[0-9]+]], TPIDR_EL0
-; CHECK: add x[[REG1:[0-9]+]], x[[BASE]], :tprel_hi12:x
-; CHECK: add x[[REG2:[0-9]+]], x[[REG1]], :tprel_lo12_nc:x
-;
-; CHECK: .LBB0_2:
-; CHECK: ldr w0, [x[[REG2]]]
-; CHECK: bl bar
-; CHECK: subs w[[REG3:[0-9]+]], w{{[0-9]+}}, #1
-; CHECK: b.ne .LBB0_2
-
-define void @test1(i32 %n) local_unnamed_addr {
-entry:
- %cmp3 = icmp sgt i32 %n, 0
- br i1 %cmp3, label %bb1, label %bb2
-
-bb1:
- br label %for.body
-
-for.body:
- %i.04 = phi i32 [ %inc, %for.body ], [ 0, %bb1 ]
- %0 = load i32, i32* @x, align 4
- tail call void @bar(i32 %0) #2
- %inc = add nuw nsw i32 %i.04, 1
- %exitcond = icmp eq i32 %inc, %n
- br i1 %exitcond, label %bb2, label %for.body
-
-bb2:
- ret void
-}
-
-; Machine CSE should combine the the mrs between the load of %x and %y.
-; CHECK-LABEL: @test2
-; CHECK: mrs x{{[0-9]+}}, TPIDR_EL0
-; CHECK-NOT: mrs x{{[0-9]+}}, TPIDR_EL0
-; CHECK: ret
-define void @test2(i32 %c) local_unnamed_addr #0 {
-entry:
- %0 = load i32, i32* @x, align 4
- tail call void @bar(i32 %0) #2
- %cmp = icmp eq i32 %c, 0
- br i1 %cmp, label %if.end, label %if.then
-
-if.then:
- %1 = load i32, i32* @y, align 4
- tail call void @bar(i32 %1) #2
- br label %if.end
-
-if.end:
- ret void
-}
-
-declare void @bar(i32) local_unnamed_addr
diff -r b5eb87bce03c -r f3f851846949 external/bsd/llvm/dist/llvm/test/CodeGen/X86/f16c-schedule.ll
--- a/external/bsd/llvm/dist/llvm/test/CodeGen/X86/f16c-schedule.ll Sun Dec 17 21:16:57 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,144 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge | FileCheck %s --check-prefix=CHECK --check-prefix=IVY
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
-
-define <4 x float> @test_vcvtph2ps_128(<8 x i16> %a0, <8 x i16> *%a1) {
-; IVY-LABEL: test_vcvtph2ps_128:
-; IVY: # BB#0:
-; IVY-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [7:1.00]
-; IVY-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
-; IVY-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; IVY-NEXT: retq # sched: [1:1.00]
-;
-; HASWELL-LABEL: test_vcvtph2ps_128:
-; HASWELL: # BB#0:
-; HASWELL-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [7:1.00]
-; HASWELL-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [4:1.00]
-; HASWELL-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; HASWELL-NEXT: retq # sched: [1:1.00]
-;
-; BTVER2-LABEL: test_vcvtph2ps_128:
-; BTVER2: # BB#0:
-; BTVER2-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [8:1.00]
-; BTVER2-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
-;
-; ZNVER1-LABEL: test_vcvtph2ps_128:
-; ZNVER1: # BB#0:
-; ZNVER1-NEXT: vcvtph2ps (%rdi), %xmm1 # sched: [12:1.00]
-; ZNVER1-NEXT: vcvtph2ps %xmm0, %xmm0 # sched: [5:1.00]
-; ZNVER1-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
-; ZNVER1-NEXT: retq # sched: [5:0.50]
- %1 = load <8 x i16>, <8 x i16> *%a1
- %2 = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %1)
- %3 = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0)
- %4 = fadd <4 x float> %2, %3
- ret <4 x float> %4
-}
-declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>)
-
-define <8 x float> @test_vcvtph2ps_256(<8 x i16> %a0, <8 x i16> *%a1) {
-; IVY-LABEL: test_vcvtph2ps_256:
-; IVY: # BB#0:
-; IVY-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [7:1.00]
-; IVY-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [3:1.00]
-; IVY-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; IVY-NEXT: retq # sched: [1:1.00]
-;
-; HASWELL-LABEL: test_vcvtph2ps_256:
-; HASWELL: # BB#0:
-; HASWELL-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [7:1.00]
-; HASWELL-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [4:1.00]
-; HASWELL-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; HASWELL-NEXT: retq # sched: [1:1.00]
-;
-; BTVER2-LABEL: test_vcvtph2ps_256:
-; BTVER2: # BB#0:
-; BTVER2-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [8:1.00]
-; BTVER2-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [3:1.00]
-; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:2.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
-;
-; ZNVER1-LABEL: test_vcvtph2ps_256:
-; ZNVER1: # BB#0:
-; ZNVER1-NEXT: vcvtph2ps (%rdi), %ymm1 # sched: [12:1.00]
-; ZNVER1-NEXT: vcvtph2ps %xmm0, %ymm0 # sched: [5:1.00]
-; ZNVER1-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
-; ZNVER1-NEXT: retq # sched: [5:0.50]
- %1 = load <8 x i16>, <8 x i16> *%a1
- %2 = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %1)
- %3 = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0)
- %4 = fadd <8 x float> %2, %3
- ret <8 x float> %4
-}
-declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>)
-
-define <8 x i16> @test_vcvtps2ph_128(<4 x float> %a0, <4 x float> %a1, <4 x i16> *%a2) {
-; IVY-LABEL: test_vcvtps2ph_128:
-; IVY: # BB#0:
-; IVY-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
-; IVY-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [7:1.00]
-; IVY-NEXT: retq # sched: [1:1.00]
-;
-; HASWELL-LABEL: test_vcvtps2ph_128:
-; HASWELL: # BB#0:
-; HASWELL-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [4:1.00]
-; HASWELL-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [8:1.00]
-; HASWELL-NEXT: retq # sched: [1:1.00]
-;
-; BTVER2-LABEL: test_vcvtps2ph_128:
-; BTVER2: # BB#0:
-; BTVER2-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [8:1.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
-;
-; ZNVER1-LABEL: test_vcvtps2ph_128:
-; ZNVER1: # BB#0:
-; ZNVER1-NEXT: vcvtps2ph $0, %xmm0, %xmm0 # sched: [5:1.00]
-; ZNVER1-NEXT: vcvtps2ph $0, %xmm1, (%rdi) # sched: [12:1.00]
-; ZNVER1-NEXT: retq # sched: [5:0.50]
- %1 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)
- %2 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a1, i32 0)
- %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- store <4 x i16> %3, <4 x i16> *%a2
- ret <8 x i16> %1
-}
-declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32)
-
-define <8 x i16> @test_vcvtps2ph_256(<8 x float> %a0, <8 x float> %a1, <8 x i16> *%a2) {
-; IVY-LABEL: test_vcvtps2ph_256:
-; IVY: # BB#0:
-; IVY-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [3:1.00]
-; IVY-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [7:1.00]
-; IVY-NEXT: vzeroupper # sched: [?:0.000000e+00]
-; IVY-NEXT: retq # sched: [1:1.00]
-;
-; HASWELL-LABEL: test_vcvtps2ph_256:
-; HASWELL: # BB#0:
-; HASWELL-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [4:1.00]
-; HASWELL-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
-; HASWELL-NEXT: vzeroupper # sched: [1:0.00]
-; HASWELL-NEXT: retq # sched: [1:1.00]
-;
-; BTVER2-LABEL: test_vcvtps2ph_256:
-; BTVER2: # BB#0:
-; BTVER2-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
-; BTVER2-NEXT: retq # sched: [4:1.00]
-;
-; ZNVER1-LABEL: test_vcvtps2ph_256:
-; ZNVER1: # BB#0:
-; ZNVER1-NEXT: vcvtps2ph $0, %ymm0, %xmm0 # sched: [5:1.00]
-; ZNVER1-NEXT: vcvtps2ph $0, %ymm1, (%rdi) # sched: [12:1.00]
-; ZNVER1-NEXT: vzeroupper # sched: [?:0.000000e+00]
-; ZNVER1-NEXT: retq # sched: [5:0.50]
- %1 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
- %2 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a1, i32 0)
- store <8 x i16> %2, <8 x i16> *%a2
- ret <8 x i16> %1
-}
-declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32)
diff -r b5eb87bce03c -r f3f851846949 external/bsd/llvm/dist/llvm/test/CodeGen/X86/lea32-schedule.ll
--- a/external/bsd/llvm/dist/llvm/test/CodeGen/X86/lea32-schedule.ll Sun Dec 17 21:16:57 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,653 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=atom | FileCheck %s --check-prefix=CHECK --check-prefix=ATOM
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
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