[src/trunk]: src/sys/dev/pci - add macros to calculate MSI MME and MMC.

[knakahara <knakahara%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/57d4b8faf6e1
branches:  trunk
changeset: 806408:57d4b8faf6e1
user:      knakahara <knakahara%NetBSD.org@localhost>
date:      Mon Feb 23 04:16:17 2015 +0000

description:
- add macros to calculate MSI MME and MMC.
- add MSI-X table offset macros.
- fix MSI-X table entry name.

diffstat:

 sys/dev/pci/pcireg.h |  14 ++++++++++----
 1 files changed, 10 insertions(+), 4 deletions(-)

diffs (41 lines):

diff -r 76cf1dddcadf -r 57d4b8faf6e1 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Mon Feb 23 00:09:30 2015 +0000
+++ b/sys/dev/pci/pcireg.h      Mon Feb 23 04:16:17 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.100 2014/11/24 07:53:43 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.101 2015/02/23 04:16:17 knakahara Exp $   */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -639,7 +639,9 @@
 #define        PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK)
 #define        PCI_MSI_CTL_64BIT_ADDR  __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK)
 #define        PCI_MSI_CTL_MME_MASK    __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK)
+#define        PCI_MSI_CTL_MME(reg)    __SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK)
 #define        PCI_MSI_CTL_MMC_MASK    __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK)
+#define        PCI_MSI_CTL_MMC(reg)    __SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK)
 #define        PCI_MSI_CTL_MSI_ENABLE  __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK)
 
 /*
@@ -1054,14 +1056,18 @@
 #define        PCI_MSIX_PBAOFFSET_MASK 0xfffffff8
 #define        PCI_MSIX_PBABIR_MASK    0x00000007
 
+#define PCI_MSIX_TABLE_ENTRY_SIZE      16
+#define PCI_MSIX_TABLE_ENTRY_ADDR_LO   0x0
+#define PCI_MSIX_TABLE_ENTRY_ADDR_HI   0x4
+#define PCI_MSIX_TABLE_ENTRY_DATA      0x8
+#define PCI_MSIX_TABLE_ENTRY_VECTCTL   0xc
 struct pci_msix_table_entry {
        uint32_t pci_msix_addr_lo;
        uint32_t pci_msix_addr_hi;
        uint32_t pci_msix_value;
-       uint32_t pci_msix_vendor_control;
+       uint32_t pci_msix_vector_control;
 };
-#define        PCI_MSIX_VENDCTL_MASK   0x00000001
-
+#define        PCI_MSIX_VECTCTL_HWMASK_MASK    0x00000001
 
 /*
  * Capability ID: 0x12