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[src/perseant-stdc-iso10646]: src/sys/arch/arm/sunxi 2360748
details: https://anonhg.NetBSD.org/src/rev/5ecf68914b47
branches: perseant-stdc-iso10646
changeset: 850667:5ecf68914b47
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Mon Jul 17 23:26:18 2017 +0000
description:
2360748
diffstat:
sys/arch/arm/sunxi/files.sunxi | 111 +++++++++++
sys/arch/arm/sunxi/sun8i_h3_ccu.c | 314 +++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu.c | 345 +++++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu.h | 331 +++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu_phase.c | 126 ++++++++++++
5 files changed, 1227 insertions(+), 0 deletions(-)
diffs (truncated from 1247 to 300 lines):
diff -r 4692cc1dfb1f -r 5ecf68914b47 sys/arch/arm/sunxi/files.sunxi
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/files.sunxi Mon Jul 17 23:26:18 2017 +0000
@@ -0,0 +1,111 @@
+# $NetBSD: files.sunxi,v 1.12.2.2 2017/07/17 23:26:18 jmcneill Exp $
+#
+# Configuration info for Allwinner sunxi family SoCs
+#
+#
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+file arch/arm/arm32/armv7_generic_space.c
+file arch/arm/arm32/armv7_generic_dma.c
+file arch/arm/arm/bus_space_a4x.S
+
+file arch/arm/sunxi/sunxi_platform.c soc_sunxi
+
+# CCU
+define sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_div.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_gate.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_nm.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_nkmp.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_phase.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_prediv.c sunxi_ccu
+
+# CCU (A31)
+device sun6ia31ccu: sunxi_ccu
+attach sun6ia31ccu at fdt with sunxi_a31_ccu
+file arch/arm/sunxi/sun6i_a31_ccu.c sunxi_a31_ccu
+
+# CCU (A83T)
+device sun8ia83tccu: sunxi_ccu
+attach sun8ia83tccu at fdt with sunxi_a83t_ccu
+file arch/arm/sunxi/sun8i_a83t_ccu.c sunxi_a83t_ccu
+
+# CCU (H3)
+device sun8ih3ccu: sunxi_ccu
+attach sun8ih3ccu at fdt with sunxi_h3_ccu
+file arch/arm/sunxi/sun8i_h3_ccu.c sunxi_h3_ccu
+
+# Misc. clock resets
+device sunxiresets
+attach sunxiresets at fdt with sunxi_resets
+file arch/arm/sunxi/sunxi_resets.c sunxi_resets
+
+# Misc. clock gates
+device sunxigates
+attach sunxigates at fdt with sunxi_gates
+file arch/arm/sunxi/sunxi_gates.c sunxi_gates
+
+# GPIO
+device sunxigpio: gpiobus
+attach sunxigpio at fdt with sunxi_gpio
+file arch/arm/sunxi/sunxi_gpio.c sunxi_gpio
+file arch/arm/sunxi/sun6i_a31_gpio.c sunxi_gpio & soc_sun6i_a31
+file arch/arm/sunxi/sun8i_a83t_gpio.c sunxi_gpio & soc_sun8i_a83t
+file arch/arm/sunxi/sun8i_h3_gpio.c sunxi_gpio & soc_sun8i_h3
+
+# UART
+attach com at fdt with sunxi_com
+file arch/arm/sunxi/sunxi_com.c sunxi_com needs-flag
+
+# SD/MMC
+device sunximmc: sdmmcbus
+attach sunximmc at fdt with sunxi_mmc
+file arch/arm/sunxi/sunxi_mmc.c sunxi_mmc
+
+# USB PHY
+device sunxiusbphy
+attach sunxiusbphy at fdt with sunxi_usbphy
+file arch/arm/sunxi/sunxi_usbphy.c sunxi_usbphy
+
+# EHCI
+attach ehci at fdt with ehci_fdt
+file dev/fdt/ehci_fdt.c ehci_fdt
+
+# OHCI
+attach ohci at fdt with ohci_fdt
+file dev/fdt/ohci_fdt.c ohci_fdt
+
+# TWI
+device sunxitwi: i2cbus, i2cexec, mvi2c
+attach sunxitwi at fdt with sunxi_twi
+file arch/arm/sunxi/sunxi_twi.c sunxi_twi
+
+# P2WI/RSB
+device sunxirsb: i2cbus, i2cexec
+attach sunxirsb at fdt with sunxi_rsb
+file arch/arm/sunxi/sunxi_rsb.c sunxi_rsb
+
+# RTC
+device sunxirtc
+attach sunxirtc at fdt with sunxi_rtc
+file arch/arm/sunxi/sunxi_rtc.c sunxi_rtc
+
+# EMAC
+device sunxiemac: arp, ether, ifnet, mii
+attach sunxiemac at fdt with sunxi_emac
+file arch/arm/sunxi/sunxi_emac.c sunxi_emac
+
+# SOC parameters
+defflag opt_soc.h SOC_SUNXI
+defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN8I_A83T: SOC_SUN8I
+defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
+defflag opt_soc.h SOC_SUN6I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN6I_A31: SOC_SUN6I
diff -r 4692cc1dfb1f -r 5ecf68914b47 sys/arch/arm/sunxi/sun8i_h3_ccu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun8i_h3_ccu.c Mon Jul 17 23:26:18 2017 +0000
@@ -0,0 +1,314 @@
+/* $NetBSD: sun8i_h3_ccu.c,v 1.8.2.2 2017/07/17 23:26:18 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * Copyright (c) 2017 Emmanuel Vadot <manu%freebsd.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.8.2.2 2017/07/17 23:26:18 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun8i_h3_ccu.h>
+
+#define PLL_PERIPH0_CTRL_REG 0x028
+#define AHB1_APB1_CFG_REG 0x054
+#define APB2_CFG_REG 0x058
+#define AHB2_CFG_REG 0x05c
+#define AHB2_CLK_CFG __BITS(1,0)
+#define AHB2_CLK_CFG_PLL_PERIPH0_2 1
+#define BUS_CLK_GATING_REG0 0x060
+#define BUS_CLK_GATING_REG2 0x068
+#define BUS_CLK_GATING_REG3 0x06c
+#define SDMMC0_CLK_REG 0x088
+#define SDMMC1_CLK_REG 0x08c
+#define SDMMC2_CLK_REG 0x090
+#define USBPHY_CFG_REG 0x0cc
+#define MBUS_RST_REG 0x0fc
+#define BUS_SOFT_RST_REG0 0x2c0
+#define BUS_SOFT_RST_REG1 0x2c4
+#define BUS_SOFT_RST_REG2 0x2c8
+#define BUS_SOFT_RST_REG3 0x2d0
+#define BUS_SOFT_RST_REG4 0x2d8
+
+static int sun8i_h3_ccu_match(device_t, cfdata_t, void *);
+static void sun8i_h3_ccu_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "allwinner,sun8i-h3-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc),
+ sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = {
+ SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0),
+ SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1),
+ SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2),
+ SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3),
+
+ SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
+ SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
+ SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
+ SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
+ SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
+ SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
+ SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
+ SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
+ SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
+ SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
+ SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3),
+ SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4),
+ SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5),
+ SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
+ SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9),
+ SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10),
+ SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11),
+ SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
+ SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20),
+ SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
+ SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1),
+ SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
+ SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20),
+};
+
+static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" };
+static const char *ahb2_parents[] = { "ahb1", "pll_periph0" };
+static const char *apb1_parents[] = { "ahb1" };
+static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
+static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
+
+static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = {
+ SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc",
+ PLL_PERIPH0_CTRL_REG, /* reg */
+ __BITS(12,8), /* n */
+ __BITS(5,4), /* k */
+ 0, /* m */
+ __BITS(17,16), /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_DIVIDE_BY_TWO),
+
+ SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents,
+ AHB1_APB1_CFG_REG, /* reg */
+ __BITS(7,6), /* prediv */
+ __BIT(3), /* prediv_sel */
+ __BITS(5,4), /* div */
+ __BITS(13,12), /* sel */
+ SUNXI_CCU_PREDIV_POWER_OF_TWO),
+
+ SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents,
+ AHB2_CFG_REG, /* reg */
+ 0, /* prediv */
+ __BIT(1), /* prediv_sel */
+ 0, /* div */
+ __BITS(1,0), /* sel */
+ SUNXI_CCU_PREDIV_DIVIDE_BY_TWO),
+
+ SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents,
+ AHB1_APB1_CFG_REG, /* reg */
+ __BITS(9,8), /* div */
+ 0, /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE),
+
+ SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents,
+ APB2_CFG_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(4,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
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