[src/trunk]: src/tests/lib/libnvmm Put correct values in the seg fields. AMD ...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ccf0578bfeb5
branches:  trunk
changeset: 838812:ccf0578bfeb5
user:      maxv <maxv%NetBSD.org@localhost>
date:      Fri Feb 01 05:32:08 2019 +0000

description:
Put correct values in the seg fields. AMD doesn't check for that, but Intel
does, so they need to be correct.

diffstat:

 tests/lib/libnvmm/h_mem_assist.c |  10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diffs (27 lines):

diff -r bab3a73c6a5b -r ccf0578bfeb5 tests/lib/libnvmm/h_mem_assist.c
--- a/tests/lib/libnvmm/h_mem_assist.c  Fri Feb 01 03:20:35 2019 +0000
+++ b/tests/lib/libnvmm/h_mem_assist.c  Fri Feb 01 05:32:08 2019 +0000
@@ -60,7 +60,7 @@
        seg->attrib.lng = 1;
        seg->attrib.def32 = 0;
        seg->attrib.gran = 1;
-       seg->limit = 0xFFFFFFFF;
+       seg->limit = 0x0000FFFF;
        seg->base = 0x00000000;
 }
 
@@ -81,10 +81,10 @@
        init_seg(&state.segs[NVMM_X64_SEG_GS], SDT_MEMRWA, GSEL(GDATA_SEL, SEL_KPL));
 
        /* Blank. */
-       init_seg(&state.segs[NVMM_X64_SEG_GDT], 0, 0x0000);
-       init_seg(&state.segs[NVMM_X64_SEG_IDT], 0, 0x0000);
-       init_seg(&state.segs[NVMM_X64_SEG_LDT], 0, 0x0000);
-       init_seg(&state.segs[NVMM_X64_SEG_TR], 0, 0x0000);
+       init_seg(&state.segs[NVMM_X64_SEG_GDT], 0, 0);
+       init_seg(&state.segs[NVMM_X64_SEG_IDT], 0, 0);
+       init_seg(&state.segs[NVMM_X64_SEG_LDT], SDT_SYSLDT, 0);
+       init_seg(&state.segs[NVMM_X64_SEG_TR], SDT_SYS386BSY, 0);
 
        /* Protected mode enabled. */
        state.crs[NVMM_X64_CR_CR0] = CR0_PG|CR0_PE|CR0_NE|CR0_TS|CR0_MP|CR0_WP|CR0_AM;