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[src/perseant-stdc-iso10646]: src/sys/arch/amd64/amd64 2302716
details: https://anonhg.NetBSD.org/src/rev/979849ca94cd
branches: perseant-stdc-iso10646
changeset: 850650:979849ca94cd
user: cherry <cherry%NetBSD.org@localhost>
date: Sun Jul 16 14:02:48 2017 +0000
description:
2302716
diffstat:
sys/arch/amd64/amd64/vector.S | 976 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 976 insertions(+), 0 deletions(-)
diffs (truncated from 980 to 300 lines):
diff -r 04689d9bb980 -r 979849ca94cd sys/arch/amd64/amd64/vector.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/amd64/amd64/vector.S Sun Jul 16 14:02:48 2017 +0000
@@ -0,0 +1,976 @@
+/* $NetBSD: vector.S,v 1.50.2.2 2017/07/16 14:02:49 cherry Exp $ */
+
+/*-
+ * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum and by Andrew Doran.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+
+#include "opt_ddb.h"
+#include "opt_multiprocessor.h"
+#include "opt_xen.h"
+#include "opt_dtrace.h"
+
+#define ALIGN_TEXT .align 16,0x90
+
+#include <machine/i8259.h>
+#include <machine/i82093reg.h>
+#include <machine/i82489reg.h>
+#include <machine/frameasm.h>
+#include <machine/segments.h>
+#include <machine/trap.h>
+#include <machine/specialreg.h>
+
+#include "ioapic.h"
+#include "lapic.h"
+#include "assym.h"
+
+#include "amd64_trap.S"
+
+/*****************************************************************************/
+
+#define __HAVE_GENERIC_SOFT_INTERRUPTS /* XXX */
+
+/*
+ * Macros for interrupt entry, call to handler, and exit.
+ *
+ * XXX
+ * The interrupt frame is set up to look like a trap frame. This may be a
+ * waste. The only handler which needs a frame is the clock handler, and it
+ * only needs a few bits. Xdoreti() needs a trap frame for handling ASTs, but
+ * it could easily convert the frame on demand.
+ *
+ * The direct costs of setting up a trap frame are two pushq's (error code and
+ * trap number), an addl to get rid of these, and pushing and popping the
+ * callee-saved registers %esi, %edi, %ebx, and %ebp twice.
+ *
+ * If the interrupt frame is made more flexible, INTR can push %eax first and
+ * decide the ipending case with less overhead, e.g., by avoiding loading the
+ * segment registers.
+ */
+
+#if NLAPIC > 0
+#ifdef MULTIPROCESSOR
+IDTVEC(recurse_lapic_ipi)
+ INTR_RECURSE_HWFRAME
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ jmp 1f
+IDTVEC_END(recurse_lapic_ipi)
+IDTVEC(intr_x2apic_ipi)
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ movl $(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
+ xorl %eax,%eax
+ xorl %edx,%edx
+ wrmsr
+ movl CPUVAR(ILEVEL),%ebx
+ cmpl $IPL_HIGH,%ebx
+ jae 2f
+ jmp 1f
+IDTVEC_END(intr_x2apic_ipi)
+IDTVEC(intr_lapic_ipi)
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ movq _C_LABEL(local_apic_va),%rbx
+ movl $0,LAPIC_EOI(%rbx)
+ movl CPUVAR(ILEVEL),%ebx
+ cmpl $IPL_HIGH,%ebx
+ jae 2f
+IDTVEC_END(intr_lapic_ipi)
+IDTVEC(resume_lapic_ipi)
+1:
+ incl CPUVAR(IDEPTH)
+ movl $IPL_HIGH,CPUVAR(ILEVEL)
+ sti
+ pushq %rbx
+ call _C_LABEL(x86_ipi_handler)
+ jmp _C_LABEL(Xdoreti)
+2:
+ orl $(1 << LIR_IPI),CPUVAR(IPENDING)
+ INTRFASTEXIT
+IDTVEC_END(resume_lapic_ipi)
+
+#if defined(DDB)
+IDTVEC(intrddb)
+1:
+ pushq $0
+ pushq $T_BPTFLT
+ INTRENTRY
+ movl $0xf,%eax
+ movq %rax,%cr8
+ movq _C_LABEL(local_apic_va),%rbx
+ movl $0,LAPIC_EOI(%rbx)
+ sti
+ call _C_LABEL(ddb_ipi)
+ xorl %eax,%eax
+ movq %rax,%cr8
+ INTRFASTEXIT
+IDTVEC_END(intrddb)
+
+IDTVEC(x2apic_intrddb)
+1:
+ pushq $0
+ pushq $T_BPTFLT
+ INTRENTRY
+ movl $0xf,%eax
+ movq %rax,%cr8
+ movl $(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
+ xorl %eax,%eax
+ xorl %edx,%edx
+ wrmsr
+ sti
+ call _C_LABEL(ddb_ipi)
+ xorl %eax,%eax
+ movq %rax,%cr8
+ INTRFASTEXIT
+IDTVEC_END(x2apic_intrddb)
+#endif /* DDB */
+#endif /* MULTIPROCESSOR */
+
+ /*
+ * Interrupt from the local APIC timer.
+ */
+IDTVEC(recurse_lapic_ltimer)
+ INTR_RECURSE_HWFRAME
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ jmp 1f
+IDTVEC_END(recurse_lapic_ltimer)
+IDTVEC(intr_x2apic_ltimer)
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ movl $(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
+ xorl %eax,%eax
+ xorl %edx,%edx
+ wrmsr
+ movl CPUVAR(ILEVEL),%ebx
+ cmpl $IPL_CLOCK,%ebx
+ jae 2f
+ jmp 1f
+IDTVEC_END(intr_x2apic_ltimer)
+IDTVEC(intr_lapic_ltimer)
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ movq _C_LABEL(local_apic_va),%rbx
+ movl $0,LAPIC_EOI(%rbx)
+ movl CPUVAR(ILEVEL),%ebx
+ cmpl $IPL_CLOCK,%ebx
+ jae 2f
+IDTVEC_END(intr_lapic_ltimer)
+IDTVEC(resume_lapic_ltimer)
+1:
+ incl CPUVAR(IDEPTH)
+ movl $IPL_CLOCK,CPUVAR(ILEVEL)
+ sti
+ pushq %rbx
+ movq %rsp,%rsi
+ xorq %rdi,%rdi
+ call _C_LABEL(lapic_clockintr)
+ jmp _C_LABEL(Xdoreti)
+2:
+ orl $(1 << LIR_TIMER),CPUVAR(IPENDING)
+ INTRFASTEXIT
+IDTVEC_END(resume_lapic_ltimer)
+#endif /* NLAPIC > 0 */
+
+#ifndef XEN
+/*
+ * TLB shootdown handler.
+ */
+IDTVEC(intr_lapic_tlb)
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ movq _C_LABEL(local_apic_va),%rax
+ movl $0,LAPIC_EOI(%rax)
+ callq _C_LABEL(pmap_tlb_intr)
+ INTRFASTEXIT
+IDTVEC_END(intr_lapic_tlb)
+
+IDTVEC(intr_x2apic_tlb)
+ pushq $0
+ pushq $T_ASTFLT
+ INTRENTRY
+ movl $(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx
+ xorl %eax,%eax
+ xorl %edx,%edx
+ wrmsr
+ callq _C_LABEL(pmap_tlb_intr)
+ INTRFASTEXIT
+IDTVEC_END(intr_x2apic_tlb)
+
+#endif /* !XEN */
+
+#define voidop(num)
+
+#ifndef XEN
+
+/*
+ * This macro defines the generic stub code. Its arguments modifiy it
+ * for specific PICs.
+ */
+
+#define INTRSTUB(name, num, early_ack, late_ack, mask, unmask, level_mask) \
+IDTVEC(recurse_ ## name ## num) ;\
+ INTR_RECURSE_HWFRAME ;\
+ subq $8,%rsp ;\
+ pushq $T_ASTFLT /* trap # for doing ASTs */ ;\
+ INTRENTRY ;\
+IDTVEC(resume_ ## name ## num) \
+ movq $IREENT_MAGIC,TF_ERR(%rsp) ;\
+ movl %ebx,%r13d ;\
+ movq CPUVAR(ISOURCES) + (num) * 8,%r14 ;\
+ movl IS_MAXLEVEL(%r14),%ebx ;\
+ jmp 1f ;\
+IDTVEC(intr_ ## name ## num) ;\
+ pushq $0 /* dummy error code */ ;\
+ pushq $T_ASTFLT /* trap # for doing ASTs */ ;\
+ INTRENTRY ;\
+ movq CPUVAR(ISOURCES) + (num) * 8,%r14 ;\
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