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[src/matt-nb8-mediatek]: src/sys/arch/arm/mediatek Initial import of Mediatek...
details: https://anonhg.NetBSD.org/src/rev/aa09a5ea0d64
branches: matt-nb8-mediatek
changeset: 851112:aa09a5ea0d64
user: matt <matt%NetBSD.org@localhost>
date: Wed Dec 13 01:06:02 2017 +0000
description:
Initial import of Mediatek written drivers and board support for Atlas board.
diffstat:
sys/arch/arm/mediatek/files.mtk | 83 ++
sys/arch/arm/mediatek/mercury_ethreg.h | 443 ++++++++++++++
sys/arch/arm/mediatek/mercury_intr.h | 52 +
sys/arch/arm/mediatek/mercury_reg.h | 117 +++
sys/arch/arm/mediatek/mtk_com.c | 166 +++++
sys/arch/arm/mediatek/mtk_eint.c | 380 ++++++++++++
sys/arch/arm/mediatek/mtk_eint.h | 99 +++
sys/arch/arm/mediatek/mtk_gpio.c | 927 +++++++++++++++++++++++++++++++
sys/arch/arm/mediatek/mtk_gpio.h | 109 +++
sys/arch/arm/mediatek/mtk_i2c.c | 985 +++++++++++++++++++++++++++++++++
sys/arch/arm/mediatek/mtk_mmc.c | 833 +++++++++++++++++++++++++++
sys/arch/arm/mediatek/mtk_musb.c | 430 ++++++++++++++
sys/arch/arm/mediatek/mtk_musb.h | 315 ++++++++++
sys/arch/arm/mediatek/mtk_platform.c | 144 ++++
sys/arch/arm/mediatek/mtk_pwm.c | 244 ++++++++
sys/arch/arm/mediatek/mtk_pwm.h | 87 ++
sys/arch/arm/mediatek/mtk_pwrap.c | 293 +++++++++
sys/arch/arm/mediatek/mtk_pwrap.h | 221 +++++++
sys/arch/arm/mediatek/mtk_spi.c | 558 ++++++++++++++++++
sys/arch/arm/mediatek/mtk_usbphy.c | 707 +++++++++++++++++++++++
20 files changed, 7193 insertions(+), 0 deletions(-)
diffs (truncated from 7273 to 300 lines):
diff -r 094ed11ff9b4 -r aa09a5ea0d64 sys/arch/arm/mediatek/files.mtk
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/mediatek/files.mtk Wed Dec 13 01:06:02 2017 +0000
@@ -0,0 +1,83 @@
+#
+# Configuration info for Mediatek ARM Peripherals
+#
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+
+file arch/arm/arm32/armv7_generic_space.c
+file arch/arm/arm32/armv7_generic_dma.c
+file arch/arm/arm/bus_space_a4x.S
+
+file arch/arm/mediatek/mtk_platform.c
+
+#file arch/arm/mediatek/mtk_board.c
+#file arch/arm/mediatek/mtk_space.c
+
+# Console parameters
+defparam opt_mtk.h CONADDR
+defparam opt_mtk.h CONSPEED
+defparam opt_mtk.h CONMODE
+defparam opt_mtk.h MEMSIZE
+defflag opt_mtk.h MTK_CONSOLE_EARLY
+
+# UART
+options COM_MTK
+
+attach com at fdt with mtk_com
+file arch/arm/mediatek/mtk_com.c mtk_com needs-flag
+
+# SPI controller (mtk spi bus)
+device mtkspi: spibus
+attach mtkspi at fdt with mtk_spi
+file arch/arm/mediatek/mtk_spi.c mtk_spi
+
+# PWM
+device mtkpwm
+attach mtkpwm at fdt with mtk_pwm
+file arch/arm/mediatek/mtk_pwm.c mtk_pwm
+
+# PWRAP
+device mtkpwrap : pwrapbus
+attach mtkpwrap at fdt with mtk_pwrap
+file arch/arm/mediatek/mtk_pwrap.c mtk_pwrap
+
+# MMC/SD controller
+options MTK_MMC
+device mtkmmc: sdmmcbus
+attach mtkmmc at fdt with mtk_mmc
+file arch/arm/mediatek/mtk_mmc.c mtk_mmc
+
+# GPIO Controller
+device mtkgpio: gpiobus
+attach mtkgpio at fdt with mtk_gpio
+file arch/arm/mediatek/mtk_gpio.c mtk_gpio
+
+# External interrupt controller
+device eint
+attach eint at fdt with mtk_eint
+file arch/arm/mediatek/mtk_eint.c mtk_eint
+
+# I2C
+device mtki2c : i2cbus, i2cexec
+attach mtki2c at fdt with mtk_i2c
+file arch/arm/mediatek/mtk_i2c.c mtk_i2c
+
+# USB2 OTG Controller
+#options MOTG_MEDIATEK
+attach motg at fdt with mtk_musb
+file arch/arm/mediatek/mtk_musb.c mtk_musb
+
+# USB PHY
+device usbphy
+attach usbphy at fdt with mtk_usbphy
+file arch/arm/mediatek/mtk_usbphy.c mtk_usbphy
+
+device mfe: ether, ifnet, arp, mii
+attach mfe at fdt with mtk_ether
+file arch/arm/mediatek/mtk_ether.c mtk_ether
diff -r 094ed11ff9b4 -r aa09a5ea0d64 sys/arch/arm/mediatek/mercury_ethreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/mediatek/mercury_ethreg.h Wed Dec 13 01:06:02 2017 +0000
@@ -0,0 +1,443 @@
+struct eth_tndesc {
+ uint32_t tn_ctl;
+ uint32_t tn_sdp;
+ uint32_t tn_vtag;
+ uint32_t tn_lso;
+};
+
+#define TN_CTL_COWN __BIT(31) // CPU Ownership
+#define TN_CTL_EOR __BIT(30) // End Of Ring
+#define TN_CTL_FS __BIT(29) // First Segment
+#define TN_CTL_LS __BIT(28) // Last Segment
+#define TN_CTL_INT __BIT(27) // Interrupt upon transmission
+#define TN_CTL_INSV __BIT(26) // Insert VLAN Tag
+#define TN_CTL_ICO __BIT(25) // Enable IP checksum offload
+#define TN_CTL_UCO __BIT(24) // Enable UDP checksum offload
+#define TN_CTL_TCO __BIT(23) // Enable TCP checksum offload
+#define TN_CTL_VTG __BIT(22) // VLAN Tag
+#define TN_CTL_ICOE __BIT(21) // IP checksum offload error
+#define TN_CTL_UCOE __BIT(20) // UDP checksum offload error
+#define TN_CTL_TCOE __BIT(19) // TCP checksum offload error
+#define TN_CTL_LSO __BIT(18) // Enable LSO function
+#define TN_CTL_INCID __BIT(17) // Increment IP ID Enable
+#define TN_CTL_SDL __BITS(15,0) // Segment Data Length
+
+#define TN_VTAG_EPID __BITS(31,16) // VLAN Tag EPID
+#define TN_VTAG_PRI __BITS(15,13) // VLAN Tag Priority
+#define TN_VTAG_CFI __BIT(12) // VLAN Tag CFI (Canonical Format Indidcator)
+#define TN_VTAG_VID __BITS(11,0) // VLAN Tag VID
+
+#define TN_LSO_MSS __BITS(31,21) // TCP MSS Value used in LSO
+#define TN_LSO_PKTLEN __BITS(20,0) // The LSO total length
+
+struct eth_fndesc {
+ uint32_t fn_sdp;
+ uint32_t fn_ctl;
+ uint32_t fn_vtag;
+ uint32_t fn__rsvrd;
+};
+
+#define FN_CTL_COWN __BIT(31) // CPU Ownership
+#define FN_CTL_EOR __BIT(30) // End Of Ring
+#define FN_CTL_FS __BIT(29) // First Segment
+#define FN_CTL_LS __BIT(28) // Last Segment
+#define FN_CTL__BIT26 __BIT(27) // Not used
+#define FN_CTL_IPV6 __BIT(26) // Bit 2 of PROT
+#define FN_CTL_OSIZE __BIT(25) // Oversized packet
+#define FN_CTL_CRCE __BIT(24) // CRC error
+#define FN_CTL_RMC __BIT(23) // Destination MAC is reserved multicast
+#define FN_CTL_HHIT __BIT(22) // Destination MAC is hit in hash table
+#define FN_CTL_MYMAC __BIT(21) // Destination MAC is My MAC
+#define FN_CTL_VTED __BIT(20) // VTAG Tag present
+#define FN_CTL_PROT01 __BITS(19,18) // Bits 0:1 of PROT
+#define FN_CTL_IPF __BIT(17) // IP Checksum failed
+#define FN_CTL_L4F __BIT(16) // Layer 4 checksum Failed
+#define FN_CTL_SDL __BITS(15,0) // Segment Data Length
+
+#define FN_VTAG_EPID __BITS(31,16) // VLAN Tag EPID
+#define FN_VTAG_PRI __BITS(15,13) // VLAN Tag Priority
+#define FN_VTAG_CFI __BIT(12) // VLAN Tag CFI (Canonical Format Indidcator)
+#define FN_VTAG_VID __BITS(11,0) // VLAN Tag VID
+
+#define PROT_UNKNOWN 7
+#define PROT_TCPV6 6 // TCP checksum
+#define PROT_UDPV6 5 // UDP checksum
+#define PROT_IPV6 4 // (IPV6 Fragment) || (IPV6 && !TCP && !UDP)
+#define PROT_TCPV4 2 // TCP & IP checksums
+#define PROT_UDPV4 1 // UDP & IP checksums
+#define PROT_IPV4 0 // (IPV4 Fragment) || (IPV4 && !TCP && !UDP)
+
+#define PHY_CTRL0 0x0000 //
+#define PHY_CTRL0_RW_DATA __BITS(31,16)
+#define PHY_CTRL0_RW_OK __BIT(15)
+#define PHY_CTRL0_CL22_RD_CMD __BIT(14)
+#define PHY_CTRL0_CL22_WR_CMD __BIT(13)
+#define PHY_CTRL0_PHY_REG __BITS(12,8)
+#define PHY_CTRL0_CL45_CMD_SEL __BITS(7,6)
+#define PHY_CTRL0_CL45_CMD __BIT(5)
+#define PHY_CTRL0_PHY_ADDR __BITS(4,0)
+#define PHY_CTRL1 0x0004 //
+#define PHY_CTRL1_PHY_ADDR_AUTO __BITS(28,24)
+#define PHY_CTRL1_SWH_CK_PD __BIT(23)
+#define PHY_CTRL1_PHY_PORT_SEL __BIT(22)
+#define PHY_CTRL1_EXT_MAC_SEL __BIT(21)
+#define PHY_CTRL1_INT_PHY_PD __BIT(19)
+#define PHY_CTRL1_RGMII_PHY __BIT(17)
+#define PHY_CTRL1_REV_MII __BIT(16)
+#define PHY_CTRL1_TXC_CHK_EN __BIT(14)
+#define PHY_CTRL1_FORCE_FC_TX __BIT(13)
+#define PHY_CTRL1_FORCE_FC_RX __BIT(12)
+#define PHY_CTRL1_FORCE_DPX __BIT(11)
+#define PHY_CTRL1_FORCE_SPD __BITS(10,9)
+#define PHY_CTRL1_AN_EN __BIT(8)
+#define PHY_CTRL1_MI_DIS __BIT(7)
+#define PHY_CTRL1_FC_TX_ST __BIT(6)
+#define PHY_CTRL1_FC_RX_ST __BIT(5)
+#define PHY_CTRL1_FDPX_ST __BIT(4)
+#define PHY_CTRL1_SPD_ST __BITS(3,2)
+#define PHY_CTRL1_SPD_ST_10 0
+#define PHY_CTRL1_SPD_ST_100 1
+#define PHY_CTRL1_SPD_ST_1000 2
+#define PHY_CTRL1_TXC_ST __BIT(1)
+#define PHY_CTRL1_LINK_ST __BIT(0)
+#define MAC_CFG 0x0008 //
+#define MAC_CFG_NIC_PD __BIT(31)
+#define MAC_CFG_WOL_PD __BIT(30)
+#define MAC_CFG_NIC_PD_RDY __BIT(29)
+#define MAC_CFG_RXDV_WAKEUP_EN __BIT(28)
+#define MAC_CFG_TXPART_WAKEUP_EN __BIT(27)
+#define MAC_CFG_TX_CKS_EN __BIT(26)
+#define MAC_CFG_RX_CKS_EN __BIT(25)
+#define MAC_CFG_ACPT_CKS_ERR __BIT(24)
+#define MAC_CFG_INS_EN __BIT(23)
+#define MAC_CFG_VLAN_STRIP __BIT(22)
+#define MAC_CFG_ACPT_CRC_ERR __BIT(21)
+#define MAC_CFG_CRC_STRIP __BIT(20)
+#define MAC_CFG_TX_AUTO_PAD __BIT(19)
+#define MAC_CFG_ACPT_LONG_PKT __BIT(18)
+#define MAC_CFG_MAC_LEN __BITS(17,16)
+#define MAC_CFG_MAC_LEN_1518 0
+#define MAC_CFG_MAC_LEN_1522 1
+#define MAC_CFG_MAC_LEN_1536 2
+#define MAC_CFG_MAC_LEN_AUTO 3
+#define MAC_CFG_UDPV6_DROP0CKSUM __BIT(15)
+#define MAC_CFG_IPG __BITS(14,10)
+#define MAC_CFG_IPG_96 0x1f
+#define MAC_CFG_IPG_88 0x1b
+#define MAC_CFG_IPG_80 0x17
+#define MAC_CFG_IPG_72 0x13
+#define MAC_CFG_IPG_64 0x0f
+#define MAC_CFG_IPG_56 0x0b
+#define MAC_CFG_IPG_48 0x07
+#define MAC_CFG_IPG_40 0x06
+#define MAC_CFG_IPG_32 0x05
+#define MAC_CFG_DONOT_SKIP __BIT(9)
+#define MAC_CFG_FAST_RETRY __BIT(8)
+#define MAC_CFG_TX_VLANTAG_AUTO_PAR __BIT(0)
+#define FC_CFG 0x000c //
+#define FC_CFG_SEND_PAUSE_TH __BITS(27,16)
+#define FC_CFG_COLCNT_CLR_MIDE __BIT(9)
+#define FC_CFG_UC_PAUSE_DIS __BIT(8)
+#define FC_CFG_BP_EN __BIT(7)
+#define FC_CFG_CRS_BP_MODE __BIT(6)
+#define FC_CFG_MAX_BP_COL_EN __BIT(5)
+#define FC_CFG_MAX_BP_COL_CNT __BITS(4,0)
+#define ARL_CFG 0x0010 //
+#define ARL_CFG_HASH_MULTICAST_ONLY __BIT(7)
+#define ARL_CFG_PRI_TAG_FIL __BIT(6)
+#define ARL_CFG_VLAN_UTAG_FIL __BIT(5)
+#define ARL_CFG_MISC_MODE __BIT(4)
+#define ARL_CFG_MY_MAC_ONLY __BIT(3)
+#define ARL_CFG_CPU_LEN_DIS __BIT(2)
+#define ARL_CFG_REV_MC_FILTER __BIT(1)
+#define ARL_CFG_HASH_ALG __BIT(0)
+#define MYMAC0_H 0x0014 // Bits [47:32] (first DA byte is mSB)
+#define MKMYMAC_H(da0,da1) \
+ (((da0) << 8)|(da1))
+#define MYMAC0_L 0x0018 // Bits [31:0]
+#define MKMYMAC_L(da2,da3,da4,da5) \
+ (((da2) << 24)|((da3) << 16)|((da4) << 8)|(da5))
+#define HASH_CTRL 0x001c //
+#define HASH_CTRL_HT_BIST_EN __BIT(31)
+#define HASH_CTRL_HT_BIST_DONE __BIT(17)
+#define HASH_CTRL_HT_BIST_OK __BIT(16)
+#define HASH_CTRL_HASH_ACC_WR_CMD __BIT(13)
+#define HASH_CTRL_HASH_BIT_DATA __BIT(12)
+#define HASH_CTRL_HASH_BIT_ADDRESS __BITS(8,0)
+#define VLAN_CTRL 0x0020 //
+#define VLAN_CTL_MY_VID3_EN __BIT(3)
+#define VLAN_CTL_MY_VID2_EN __BIT(2)
+#define VLAN_CTL_MY_VID1_EN __BIT(1)
+#define VLAN_CTL_MY_VID0_EN __BIT(0)
+#define VLAN_ID_01 0x0024 //
+#define VLAN_ID_MYVID1 __BITS(27,16)
+#define VLAN_ID_MYVID0 __BITS(11,0)
+#define VLAN_ID_23 0x0028 //
+#define VLAN_ID_MYVID2 __BITS(27,16)
+#define VLAN_ID_MYVID3 __BITS(11,0)
+#define DUMMY_CTRL 0x002c //
+#define DUMMY_CTRL_TXC_EXIST_EN __BIT(4)
+#define DUMMY_CTRL_WR_CLR_MIB __BIT(3)
+#define DUMMY_CTRL_NO_COL_PIN __BIT(2)
+#define DUMMY_CTRL_TX_RX_PD_RDY __BIT(1)
+#define DUMMY_CTRL_MDIO_CMD_DONE __BIT(0)
+#define DMA_CFG 0x0030 //
+#define DMA_CFG_RX_OFFSET_2B_DIS __BIT(16)
+#define DMA_CFG_TX_CKSERR_WRKB_DIS __BIT(8)
+#define DMA_CFG_TX_POLL_PERIOD __BIT(7,6)
+#define DMA_CFG_XX_POLL_PERIOD_1US 0
+#define DMA_CFG_XX_POLL_PERIOD_10US 1
+#define DMA_CFG_XX_POLL_PERIOD_100US 2
+#define DMA_CFG_XX_POLL_PERIOD_1000US 3
+#define DMA_CFG_TX_POLL_END __BIT(5)
+#define DMA_CFG_TX_SUSPEND __BIT(4)
+#define DMA_CFG_RX_POLL_PERIOD __BITS(3,2)
+#define DMA_CFG_RX_POLL_EN __BIT(1)
+#define DMA_CFG_RX_SUSPEND __BIT(0)
+#define TX_DMA_CTRL 0x0034 //
+#define TX_DMA_CTRL_TX_EN __BIT(3)
+#define TX_DMA_CTRL_TX_RESUME __BIT(2)
+#define TX_DMA_CTRL_TX_STOP __BIT(1)
+#define TX_DMA_CTRL_TX_START __BIT(0)
+#define RX_DMA_CTRL 0x0038 //
+#define RX_DMA_CTRL_TX_EN __BIT(3)
+#define RX_DMA_CTRL_TX_RESUME __BIT(2)
+#define RX_DMA_CTRL_TX_STOP __BIT(1)
+#define RX_DMA_CTRL_TX_START __BIT(0)
+#define TX_DPTR 0x003c // 16-byte aligned
+#define RX_DPTR 0x0040 // 16-byte aligned
+#define TX_BASE_ADDR 0x0044 //
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