Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/netbsd-8]: src Pull up following revision(s) (requested by msaitoh in ti...



details:   https://anonhg.NetBSD.org/src/rev/f492c4ceda33
branches:  netbsd-8
changeset: 851141:f492c4ceda33
user:      martin <martin%NetBSD.org@localhost>
date:      Tue Nov 21 15:03:20 2017 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #365):
        sys/arch/x86/include/specialreg.h: revision 1.99
        usr.sbin/cpuctl/arch/i386.c: revision 1.75
        usr.sbin/cpuctl/arch/i386.c: revision 1.76
        usr.sbin/cpuctl/arch/i386.c: revision 1.77
        usr.sbin/cpuctl/arch/i386.c: revision 1.78
        sys/arch/x86/x86/identcpu.c: revision 1.56
        sys/arch/x86/x86/identcpu.c: revision 1.57
        sys/arch/x86/x86/cpu_topology.c: revision 1.10
        sys/arch/x86/include/specialreg.h: revision 1.100
        sys/arch/x86/include/specialreg.h: revision 1.101
        sys/arch/x86/include/specialreg.h: revision 1.102
        sys/arch/x86/include/specialreg.h: revision 1.103
        sys/arch/x86/include/specialreg.h: revision 1.104
        sys/arch/x86/include/specialreg.h: revision 1.105
Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.
Fix typo in comment
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.
  Define CPUID Fn00000001 %ebx bits and use them. No functional change.
Set ci->ci_cflush_lsize correctly. This bug was added in the last commit(1.56).
  Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
        AVX512_IFMA
        AVX512_VBMI
        AVX512_VBMI2
        GFNI
        VAES
        VPCLMULQDQ
        AVX512_VNNI
        AVX512_BITALG
        AVX512_VPOPCNTDQ
        AVX512_4VNNIW
        AVX512_4FMAPS
- Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
   AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.
Update from the latest Intel SDM:
  0x5c: Atom (Goldmont)
  0x5f: Atom (Goldmont, Denverton)
  0x7a: Atom (Goldmont Plus)
  Add Turbo Boost Max Technology 3.0 bit.
Update from Intel SDM:
  0x55: Xeon Scalable (Skylake)
  0x57: Xeon Phi [357]200 (Knights Landing)
  0x66: Future Core (Cannon Lake)
  0x85: Future Xeon Phi (Knights Mill)
  Add the following bits in AMD Fn8000000a %edx features (SVM features):
        PFThreshold (PAUSE filter threshold)
        AVIC (AMD virtual interrupt controller)
        V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
        vGIF (virtualized GIF)

diffstat:

 sys/arch/x86/include/specialreg.h |  58 +++++++++++++++++++++++++++++++-------
 sys/arch/x86/x86/cpu_topology.c   |   6 ++--
 sys/arch/x86/x86/identcpu.c       |   9 +++--
 usr.sbin/cpuctl/arch/i386.c       |  31 ++++++++++++--------
 4 files changed, 73 insertions(+), 31 deletions(-)

diffs (285 lines):

diff -r 38929693f50a -r f492c4ceda33 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Tue Nov 21 14:51:04 2017 +0000
+++ b/sys/arch/x86/include/specialreg.h Tue Nov 21 15:03:20 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.98 2017/05/15 04:02:52 msaitoh Exp $  */
+/*     $NetBSD: specialreg.h,v 1.98.2.1 2017/11/21 15:03:20 martin Exp $       */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -130,7 +130,7 @@
 #define CPUID_DE       0x00000004      /* has debugging extension */
 #define CPUID_PSE      0x00000008      /* has 4MB page size extension */
 #define CPUID_TSC      0x00000010      /* has time stamp counter */
-#define CPUID_MSR      0x00000020      /* has mode specific registers */
+#define CPUID_MSR      0x00000020      /* has model specific registers */
 #define CPUID_PAE      0x00000040      /* has phys address extension */
 #define CPUID_MCE      0x00000080      /* has machine check exception */
 #define CPUID_CX8      0x00000100      /* has CMPXCHG8B instruction */
@@ -248,6 +248,12 @@
                && (CPUID_TO_BASEFAMILY(cpuid) != 0x06)         \
                ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
 
+/* CPUID Fn00000001 %ebx */
+#define        CPUID_BRAND_INDEX       __BITS(7,0)
+#define        CPUID_CLFUSH_SIZE       __BITS(15,8)
+#define        CPUID_HTT_CORES         __BITS(23,16)
+#define        CPUID_LOCAL_APIC_ID     __BITS(31,24)
+
 /*
  * Intel Deterministic Cache Parameter Leaf
  * Fn0000_0004
@@ -293,12 +299,13 @@
 #define CPUID_DSPM_HWP_EPP __BIT(10)   /* HWP Energy Performance Preference */
 #define CPUID_DSPM_HWP_PLR __BIT(11)   /* HWP Package Level Request */
 #define CPUID_DSPM_HDC __BIT(13)       /* Hardware Duty Cycling */
+#define CPUID_DSPM_TBMT3 __BIT(14)     /* Turbo Boost Max Technology 3.0 */
 
 #define CPUID_DSPM_FLAGS       "\20" \
        "\1" "DTS"      "\2" "IDA"      "\3" "ARAT"                     \
        "\5" "PLN"      "\6" "ECMD"     "\7" "PTM"      "\10" "HWP"     \
        "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
-                       "\16" "HDC"
+                       "\16" "HDC"     "\17" "TBM3"
 
 /*
  * Intel Digital Thermal Sensor and
@@ -339,6 +346,7 @@
 #define CPUID_SEF_RDSEED       __BIT(18)
 #define CPUID_SEF_ADX          __BIT(19)
 #define CPUID_SEF_SMAP         __BIT(20)
+#define CPUID_SEF_AVX512_IFMA  __BIT(21)
 #define CPUID_SEF_CLFLUSHOPT   __BIT(23)
 #define CPUID_SEF_CLWB         __BIT(24)
 #define CPUID_SEF_PT           __BIT(25)
@@ -355,24 +363,41 @@
        "\11" "BMI2"    "\12" "ERMS"    "\13" "INVPCID" "\14" "RTM"     \
        "\15" "QM"      "\16" "FPUCSDS" "\17" "MPX"     "\20" "PQE"     \
        "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX"     \
-       "\25" "SMAP"                                    "\30" "CLFLUSHOPT" \
+       "\25" "SMAP"    "\26" "AVX512_IFMA"             "\30" "CLFLUSHOPT" \
        "\31" "CLWB"    "\32" "PT"      "\33" "AVX512PF" "\34" "AVX512ER" \
        "\35" "AVX512CD""\36" "SHA"     "\37" "AVX512BW" "\40" "AVX512VL"
 
 /* %ecx */
 #define CPUID_SEF_PREFETCHWT1  __BIT(0)
+#define CPUID_SEF_AVX512_VBMI  __BIT(1)
 #define CPUID_SEF_UMIP         __BIT(2)
 #define CPUID_SEF_PKU          __BIT(3)
 #define CPUID_SEF_OSPKE                __BIT(4)
+#define CPUID_SEF_AVX512_VBMI2 __BIT(6)
+#define CPUID_SEF_GFNI         __BIT(8)
+#define CPUID_SEF_VAES         __BIT(9)
+#define CPUID_SEF_VPCLMULQDQ   __BIT(10)
+#define CPUID_SEF_AVX512_VNNI  __BIT(11)
+#define CPUID_SEF_AVX512_BITALG        __BIT(12)
+#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
 #define CPUID_SEF_RDPID                __BIT(22)
 #define CPUID_SEF_SGXLC                __BIT(30)
 
 #define CPUID_SEF_FLAGS1       "\20" \
-       "\1" "PREFETCHWT1"              "\3" "UMIP"     "\4" "PKU"      \
-       "\5" "OSPKE"                                                    \
+       "\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU"    \
+       "\5" "OSPKE"                    "\7" "AVX512_VBMI2"             \
+       "\11" "GFNI"    "\12" "VAES"    "\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\
+       "\15" "AVX512_BITALG"           "\17" "AVX512_VPOPCNTDQ"        \
                                        "\27" "RDPID"                   \
                                        "\37" "SGXLC"
 
+/* %edx */
+#define CPUID_SEF_AVX512_4VNNIW        __BIT(2)
+#define CPUID_SEF_AVX512_4FMAPS        __BIT(3)
+
+#define CPUID_SEF_FLAGS2       "\20" \
+                               "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS"
+
 /*
  * CPUID Processor extended state Enumeration Fn0000000d
  *
@@ -514,13 +539,18 @@
 #define CPUID_AMD_SVM_FlushByASID      0x00000040
 #define CPUID_AMD_SVM_DecodeAssist     0x00000080
 #define CPUID_AMD_SVM_PauseFilter      0x00000400
+#define CPUID_AMD_SVM_PFThreshold      0x0x001000 /* PAUSE filter threshold */
+#define CPUID_AMD_SVM_AVIC             0x00002000 /* AMD Virtual intr. ctrl */
+#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD  0x00008000 /* Virtual VM{SAVE/LOAD} */
+#define CPUID_AMD_SVM_vGIF             0x00010000 /* Virtualized GIF */
 #define CPUID_AMD_SVM_FLAGS     "\20" \
-       "\1" "NP"       "\2" "LbrVirt"  "\3" "SVML"     "\4" "NRIPS" \
-       "\5" "TSCRate"  "\6" "VMCBCleanBits" \
-               "\7" "FlushByASID"      "\10" "DecodeAssist" \
+       "\1" "NP"       "\2" "LbrVirt"  "\3" "SVML"     "\4" "NRIPS"    \
+       "\5" "TSCRate"  "\6" "VMCBCleanBits"                            \
+                               "\7" "FlushByASID" "\10" "DecodeAssist" \
        "\11" "B08"     "\12" "B09"     "\13" "PauseFilter" "\14" "B11" \
-       "\15" "B12"     "\16" "B13"     "\17" "B17"     "\20" "B18" \
-       "\21" "B19"
+       "\15" "PFThreshold" "\16" "AVIC" "\17" "B14"                    \
+                                               "\20" "V_VMSAVE_VMLOAD" \
+       "\21" "VGIF"
 
 /*
  * Centaur Extended Feature flags
@@ -554,6 +584,11 @@
 #define        APICBASE_BSP            0x00000100      /* boot processor */
 #define        APICBASE_EXTD           0x00000400      /* x2APIC mode */
 #define        APICBASE_EN             0x00000800      /* software enable */
+/*
+ * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're
+ * only interested in the initial value, which is guaranteed to fit the
+ * first 32 bits. So this macro is fine.
+ */
 #define        APICBASE_PHYSADDR       0xfffff000      /* physical address */
 #define MSR_EBL_CR_POWERON     0x02a
 #define MSR_EBC_FREQUENCY_ID   0x02c   /* PIV only */
@@ -732,6 +767,7 @@
 #define        EFER_SVME       0x00001000      /* Secure Virtual Machine En. */
 #define        EFER_LMSLE      0x00002000      /* Long Mode Segment Limit E. */
 #define        EFER_FFXSR      0x00004000      /* Fast FXSAVE/FXRSTOR En. */
+#define        EFER_TCE        0x00008000      /* Translation Cache Ext. */
 
 #define MSR_STAR       0xc0000081              /* 32 bit syscall gate addr */
 #define MSR_LSTAR      0xc0000082              /* 64 bit syscall gate addr */
diff -r 38929693f50a -r f492c4ceda33 sys/arch/x86/x86/cpu_topology.c
--- a/sys/arch/x86/x86/cpu_topology.c   Tue Nov 21 14:51:04 2017 +0000
+++ b/sys/arch/x86/x86/cpu_topology.c   Tue Nov 21 15:03:20 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu_topology.c,v 1.9 2014/02/22 17:48:08 dsl Exp $     */
+/*     $NetBSD: cpu_topology.c,v 1.9.22.1 2017/11/21 15:03:20 martin Exp $     */
 
 /*-
  * Copyright (c) 2009 Mindaugas Rasiukevicius <rmind at NetBSD org>,
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.9 2014/02/22 17:48:08 dsl Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.9.22.1 2017/11/21 15:03:20 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/bitops.h>
@@ -81,7 +81,7 @@
        if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
                /* Maximum number of LPs sharing a cache (ebx[23:16]). */
                x86_cpuid(1, descs);
-               lp_max = (descs[1] >> 16) & 0xff;
+               lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
        } else {
                lp_max = 1;
        }
diff -r 38929693f50a -r f492c4ceda33 sys/arch/x86/x86/identcpu.c
--- a/sys/arch/x86/x86/identcpu.c       Tue Nov 21 14:51:04 2017 +0000
+++ b/sys/arch/x86/x86/identcpu.c       Tue Nov 21 15:03:20 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: identcpu.c,v 1.55 2017/05/23 08:48:34 nonaka Exp $     */
+/*     $NetBSD: identcpu.c,v 1.55.2.1 2017/11/21 15:03:20 martin Exp $ */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55 2017/05/23 08:48:34 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.1 2017/11/21 15:03:20 martin Exp $");
 
 #include "opt_xen.h"
 
@@ -847,8 +847,9 @@
 
                /* CLFLUSH line size is next 8 bits */
                if (ci->ci_feat_val[0] & CPUID_CFLUSH)
-                       ci->ci_cflush_lsize = ((miscbytes >> 8) & 0xff) << 3;
-               ci->ci_initapicid = (miscbytes >> 24) & 0xff;
+                       ci->ci_cflush_lsize
+                           = __SHIFTOUT(miscbytes, CPUID_CLFUSH_SIZE) << 3;
+               ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID);
        }
 
        /*
diff -r 38929693f50a -r f492c4ceda33 usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c       Tue Nov 21 14:51:04 2017 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c       Tue Nov 21 15:03:20 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i386.c,v 1.74 2016/10/11 04:16:28 msaitoh Exp $        */
+/*     $NetBSD: i386.c,v 1.74.6.1 2017/11/21 15:03:20 martin Exp $     */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74 2016/10/11 04:16:28 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.1 2017/11/21 15:03:20 martin Exp $");
 #endif /* not lint */
 
 #include <sys/types.h>
@@ -371,15 +371,17 @@
                                [0x4d] = "Atom C2000",
                                [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
                                [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
-                               [0x55] = "Future Xeon",
+                               [0x55] = "Xeon Scalable (Skylake)",
                                [0x56] = "Xeon D-1500 (Broadwell)",
-                               [0x57] = "Xeon Phi [357]200",
+                               [0x57] = "Xeon Phi [357]200 (Knights Landing)",
                                [0x5a] = "Atom E3500",
-                               [0x5c] = "Next Atom (Goldmont)",
+                               [0x5c] = "Atom (Goldmont)",
                                [0x5d] = "Atom X3-C3000 (Silvermont)",
                                [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
-                               [0x5f] = "Future Atom (Denverton)",
-                               [0x85] = "Future Xeon Phi",
+                               [0x5f] = "Atom (Goldmont, Denverton)",
+                               [0x66] = "Future Core (Cannon Lake)",
+                               [0x7a] = "Atom (Goldmont Plus)",
+                               [0x85] = "Future Xeon Phi (Knights Mill)",
                                [0x8e] = "7th gen Core (Kaby Lake)",
                                [0x9e] = "7th gen Core (Kaby Lake)",
                        },
@@ -1506,9 +1508,9 @@
        ci->ci_model = CPUID_TO_MODEL(ci->ci_signature);
 
        /* Brand is low order 8 bits of ebx */
-       ci->ci_brand_id = descs[1] & 0xff;
+       ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX);
        /* Initial local APIC ID */
-       ci->ci_initapicid = (descs[1] >> 24) & 0xff;
+       ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID);
 
        ci->ci_feat_val[1] = descs[2];
        ci->ci_feat_val[0] = descs[3];
@@ -1668,7 +1670,7 @@
 
        if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
                x86_cpuid(1, descs);
-               lp_max = (descs[1] >> 16) & 0xff;
+               lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
        }
        if (ci->ci_cpuid_level >= 4) {
                x86_cpuid2(4, 0, descs);
@@ -1892,7 +1894,12 @@
 
        print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK,
            ci->ci_feat_val[4]);
-
+       if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
+               print_bits(cpuname, "features5", CPUID_SEF_FLAGS,
+                   ci->ci_feat_val[5]);
+       if (cpu_vendor == CPUVENDOR_INTEL)
+               print_bits(cpuname, "features6", CPUID_SEF_FLAGS1,
+                   ci->ci_feat_val[6]);
        print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]);
        print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS,
            ci->ci_feat_val[8]);
@@ -1977,8 +1984,6 @@
                        case 7:
                                aprint_verbose("%s: SEF highest subleaf %08x\n",
                                    cpuname, data[0]);
-                               print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS,
-                                   data[1]);
                                break;
 #if 0
                        default:



Home | Main Index | Thread Index | Old Index