Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/arm/marvell Remove #ifdef ARMADAXP. It is OK !ARMA...
details: https://anonhg.NetBSD.org/src/rev/79f062b35236
branches: trunk
changeset: 790262:79f062b35236
user: kiyohara <kiyohara%NetBSD.org@localhost>
date: Mon Sep 30 13:19:28 2013 +0000
description:
Remove #ifdef ARMADAXP. It is OK !ARMADAXP.
Add some ARMADAXP devices to peripheral list.
And sort and reorder list.
diffstat:
sys/arch/arm/marvell/mvsoc.c | 341 ++++++++++++++++++++++++++++--------------
1 files changed, 229 insertions(+), 112 deletions(-)
diffs (truncated from 508 to 300 lines):
diff -r 7e4b5ce953e9 -r 79f062b35236 sys/arch/arm/marvell/mvsoc.c
--- a/sys/arch/arm/marvell/mvsoc.c Mon Sep 30 13:15:46 2013 +0000
+++ b/sys/arch/arm/marvell/mvsoc.c Mon Sep 30 13:19:28 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.12 2013/06/03 14:50:59 rkujawa Exp $ */
+/* $NetBSD: mvsoc.c,v 1.13 2013/09/30 13:19:28 kiyohara Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.12 2013/06/03 14:50:59 rkujawa Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.13 2013/09/30 13:19:28 kiyohara Exp $");
#include "opt_cputypes.h"
#include "opt_mvsoc.h"
@@ -45,11 +45,10 @@
#include <arm/marvell/mvsocvar.h>
#include <arm/marvell/orionreg.h>
#include <arm/marvell/kirkwoodreg.h>
+#include <arm/marvell/mv78xx0reg.h>
+#include <arm/marvell/armadaxpreg.h>
-#if defined(ARMADAXP)
-#include <evbarm/armadaxp/armadaxpreg.h>
-#include <evbarm/marvell/marvellreg.h>
-#endif
+#include <uvm/uvm.h>
#include "locators.h"
@@ -68,10 +67,8 @@
uint32_t mvPclk, mvSysclk, mvTclk = 0;
int nwindow = 0, nremap = 0;
static vaddr_t regbase = 0xffffffff, dsc_base, pex_base;
+vaddr_t misc_base;
vaddr_t mlmb_base;
-#if defined(ARMADAXP)
-vaddr_t misc_base;
-#endif
void (*mvsoc_intr_init)(void);
@@ -183,6 +180,56 @@
{ KIRKWOOD_TAG_CRYPT,
KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT },
#endif
+
+#if defined(MV78XX0)
+ { MV78XX0_TAG_DEVICE_CS0,
+ MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS },
+ { MV78XX0_TAG_DEVICE_CS1,
+ MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS },
+ { MV78XX0_TAG_DEVICE_CS2,
+ MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS },
+ { MV78XX0_TAG_DEVICE_CS3,
+ MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS },
+ { MV78XX0_TAG_DEVICE_BOOTCS,
+ MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS },
+ { MV78XX0_TAG_SPI,
+ MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS },
+ { MV78XX0_TAG_PEX0_MEM,
+ MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX01_MEM,
+ MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX02_MEM,
+ MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX03_MEM,
+ MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX0_IO,
+ MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX01_IO,
+ MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX02_IO,
+ MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX03_IO,
+ MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX },
+ { MV78XX0_TAG_PEX1_MEM,
+ MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_PEX11_MEM,
+ MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_PEX12_MEM,
+ MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_PEX13_MEM,
+ MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_PEX1_IO,
+ MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_PEX11_IO,
+ MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_PEX12_IO,
+ MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_PEX13_IO,
+ MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 },
+ { MV78XX0_TAG_CRYPT,
+ MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT },
+#endif
+
#if defined(ARMADAXP)
{ ARMADAXP_TAG_PEX00_MEM,
ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 },
@@ -302,7 +349,9 @@
uint32_t clkpwr_bit;
} mvsoc_periphs[] = {
#if defined(ORION)
- { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+#define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ)
+
+ { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -310,7 +359,7 @@
{ ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
{ ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT },
- { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -323,7 +372,7 @@
{ ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
{ ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR },
- { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -334,7 +383,7 @@
{ ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT },
{ ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
- { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -346,7 +395,7 @@
{ ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT },
{ ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
- { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -359,7 +408,7 @@
{ ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR },
{ ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
- { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -370,12 +419,12 @@
{ ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR },
{ ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
- { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI },
{ ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
- { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -386,7 +435,7 @@
{ ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT },
{ ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
- { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -394,7 +443,7 @@
{ ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT },
{ ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT },
- { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR },
{ ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 },
{ ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 },
{ ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 },
@@ -407,7 +456,9 @@
#endif
#if defined(KIRKWOOD)
- { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+#define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ)
+
+ { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR },
{ KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0},
{ KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT },
{ KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT },
@@ -420,7 +471,7 @@
{ KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT },
{ KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT },
- { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR },
{ KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0},
{ KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT },
{ KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT },
@@ -435,7 +486,7 @@
{ KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA },
{ KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT },
- { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR },
{ KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0},
{ KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT },
{ KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT },
@@ -458,7 +509,7 @@
{ KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT,
MVSOC_MLMB_CLKGATING_BIT(4) },
- { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT },
+ { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR },
{ KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0},
{ KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT },
{ KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT },
@@ -478,101 +529,171 @@
#endif
#if defined(MV78XX0)
- { MV78XX0(MV78100), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT },
- { MV78XX0(MV78100), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 },
- { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT },
- { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT },
- { MV78XX0(MV78100), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI },
- :
+ { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 },
+ { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 },
+ { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 },
+ { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 },
+ { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 },
+ { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 },
+ { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 },
+ { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 },
+ { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT },
+ { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT },
+ { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA },
- { MV78XX0(MV78200), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT },
- { MV78XX0(MV78200), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 },
- { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT },
- { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT },
- { MV78XX0(MV78200), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI },
- :
+ { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 },
+ { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 },
+ { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 },
+ { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 },
+ { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 },
+ { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 },
+ { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 },
+ { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 },
+ { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT },
+ { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT },
+ { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT },
+ { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT },
+ { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA },
#endif
#if defined(ARMADAXP)
{ ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
- { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT },
- { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT },
- { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT },
- { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT },
- { ARMADAXP(MV78130), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT },
- { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT },
- { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT },
- { ARMADAXP(MV78130), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00},
- { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01},
- { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02},
- { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03},
- { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE, ARMADAXP_IRQ_SDIO},
+ { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
+ { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 },
+ { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 },
+ { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 },
+ { ARMADAXP(MV78130), "mvsocrtc",0, ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC },
+ { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 },
+ { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 },
+ { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT },
+ { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT },
+ { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 },
+ { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 },
+ { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 },
+ { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 },
+ { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 },
Home |
Main Index |
Thread Index |
Old Index