[src/trunk]: src/sys/dev/pci - Add PCie Link Activation ECN.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/020205a0d504
branches:  trunk
changeset: 829449:020205a0d504
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Thu Feb 01 09:09:14 2018 +0000

description:
- Add PCie Link Activation ECN.
- Use macro.
- KNF.

diffstat:

 sys/dev/pci/pci_subr.c |  27 ++++++++++++++++++++++-----
 sys/dev/pci/pcireg.h   |   7 ++++++-
 2 files changed, 28 insertions(+), 6 deletions(-)

diffs (119 lines):

diff -r 0349ef72fda0 -r 020205a0d504 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c    Thu Feb 01 08:18:47 2018 +0000
+++ b/sys/dev/pci/pci_subr.c    Thu Feb 01 09:09:14 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci_subr.c,v 1.199 2018/02/01 08:18:47 msaitoh Exp $   */
+/*     $NetBSD: pci_subr.c,v 1.200 2018/02/01 09:09:14 msaitoh Exp $   */
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.199 2018/02/01 08:18:47 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.200 2018/02/01 09:09:14 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -1769,10 +1769,10 @@
        /* Capability Register */
        reg = regs[o2i(capoff)];
        printf("    Capability register: 0x%04x\n", reg >> 16);
-       pciever = (unsigned int)((reg & 0x000f0000) >> 16);
+       pciever = (unsigned int)(PCIE_XCAP_VER(reg));
        printf("      Capability version: %u\n", pciever);
        printf("      Device type: ");
-       switch ((reg & 0x00f00000) >> 20) {
+       switch (PCIE_XCAP_TYPE(reg)) {
        case PCIE_XCAP_TYPE_PCIE_DEV:   /* 0x0 */
                printf("PCI Express Endpoint device\n");
                check_upstreamport = true;
@@ -3634,7 +3634,7 @@
        printf("    Lane Error Status register: 0x%08x\n", reg);
 
        /* Get Max Link Width */
-       if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)){
+       if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
                reg = regs[o2i(pcie_capoff + PCIE_LCAP)];
                maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
        } else {
@@ -3873,6 +3873,7 @@
 {
        pcireg_t reg;
        int scale, val;
+       int pcie_capoff;
 
        printf("\n  L1 PM Substates\n");
 
@@ -3883,6 +3884,14 @@
        onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12);
        onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11);
        onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM);
+       /* The Link Activation Supported bit is only for Downstream Port */
+       if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
+               uint32_t t = regs[o2i(pcie_capoff)];
+
+               if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN))
+                       onoff("Link Activation Supported", reg,
+                           PCI_L1PM_CAP_LA);
+       }
        printf("      Port Common Mode Restore Time: %uus\n",
            (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT));
        scale = pci_conf_l1pm_cap_tposcale(
@@ -3900,6 +3909,8 @@
        onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN);
        onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN);
        onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN);
+       onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE);
+       onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA);
        printf("      Common Mode Restore Time: %uus\n",
            (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT));
        scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE));
@@ -3916,6 +3927,12 @@
                printf("unknown\n");
        else
                printf("%dus\n", val * scale);
+
+       if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) {
+               reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];
+               printf("    L1 PM Substates Status register: 0x%08x\n", reg);
+               onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA);
+       }
 }
 
 static void
diff -r 0349ef72fda0 -r 020205a0d504 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Thu Feb 01 08:18:47 2018 +0000
+++ b/sys/dev/pci/pcireg.h      Thu Feb 01 09:09:14 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.136 2017/12/18 04:48:28 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.137 2018/02/01 09:09:14 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -2041,6 +2041,7 @@
 #define        PCI_L1PM_CAP_ASPM12     __BIT(2)        /* ASPM L1.2 Supported */
 #define        PCI_L1PM_CAP_ASPM11     __BIT(3)        /* ASPM L1.1 Supported */
 #define        PCI_L1PM_CAP_L1PM       __BIT(4)        /* L1 PM Substates Supported */
+#define        PCI_L1PM_CAP_LA __BIT(5)                /* Link Activation Supported */
 #define        PCI_L1PM_CAP_PCMRT      __BITS(15, 8) /*Port Common Mode Restore Time*/
 #define        PCI_L1PM_CAP_PTPOSCALE  __BITS(17, 16)  /* Port T_POWER_ON Scale */
 #define        PCI_L1PM_CAP_PTPOVAL    __BITS(23, 19)  /* Port T_POWER_ON Value */
@@ -2049,12 +2050,16 @@
 #define        PCI_L1PM_CTL1_PCIPM11_EN __BIT(1)       /* PCI-PM L1.1 Enable */
 #define        PCI_L1PM_CTL1_ASPM12_EN __BIT(2)        /* ASPM L1.2 Enable */
 #define        PCI_L1PM_CTL1_ASPM11_EN __BIT(3)        /* ASPM L1.1 Enable */
+#define        PCI_L1PM_CTL1_LAIE      __BIT(4)        /* Link Activation Int. En. */
+#define        PCI_L1PM_CTL1_LA        __BIT(5)        /* Link Activation Control */
 #define        PCI_L1PM_CTL1_CMRT      __BITS(15, 8)   /* Common Mode Restore Time */
 #define        PCI_L1PM_CTL1_LTRTHVAL  __BITS(25, 16)  /* LTR L1.2 THRESHOLD Value */
 #define        PCI_L1PM_CTL1_LTRTHSCALE __BITS(31, 29) /* LTR L1.2 THRESHOLD Scale */
 #define        PCI_L1PM_CTL2   0x0c    /* Control Register 2 */
 #define        PCI_L1PM_CTL2_TPOSCALE  __BITS(1, 0)    /* T_POWER_ON Scale */
 #define        PCI_L1PM_CTL2_TPOVAL    __BITS(7, 3)    /* T_POWER_ON Value */
+#define        PCI_L1PM_STAT   0x10    /* Status Register */
+#define        PCI_L1PM_STAT_LA        __BIT(0)        /* Link Activation Status */
 
 /*
  * Extended capability ID: 0x001f