[src/trunk]: src/sys/arch/arm/arm Spell invalidate correctly in comments. No...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/aa1b76ea595f
branches:  trunk
changeset: 825450:aa1b76ea595f
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sat Jul 15 06:20:22 2017 +0000

description:
Spell invalidate correctly in comments.  No functional change.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_armv6.S |  10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diffs (38 lines):

diff -r dfe2a56a2326 -r aa1b76ea595f sys/arch/arm/arm/cpufunc_asm_armv6.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv6.S      Sat Jul 15 05:46:09 2017 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv6.S      Sat Jul 15 06:20:22 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_armv6.S,v 1.7 2014/08/01 05:53:31 skrll Exp $      */
+/*     $NetBSD: cpufunc_asm_armv6.S,v 1.8 2017/07/15 06:20:22 skrll Exp $      */
 
 /*
  * Copyright (c) 2002, 2005 ARM Limited
@@ -100,7 +100,7 @@
 ENTRY(armv6_dcache_wbinv_range)
        add     r1, r1, r0
        sub     r1, r1, #1
-       mcrr    p15, 0, r1, r0, c14     /* clean and invaliate D cache range */
+       mcrr    p15, 0, r1, r0, c14     /* clean and invalidate D cache range */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
        RET
 END(armv6_dcache_wbinv_range)
@@ -114,7 +114,7 @@
 ENTRY(armv6_dcache_inv_range)
        add     r1, r1, r0
        sub     r1, r1, #1
-       mcrr    p15, 0, r1, r0, c6      /* invaliate D cache range */
+       mcrr    p15, 0, r1, r0, c6      /* invalidate D cache range */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
        RET
 END(armv6_dcache_inv_range)
@@ -123,8 +123,8 @@
 ENTRY(armv6_idcache_wbinv_range)
        add     r1, r1, r0
        sub     r1, r1, #1
-       mcrr    p15, 0, r1, r0, c5      /* invaliate I cache range */
-       mcrr    p15, 0, r1, r0, c14     /* clean & invaliate D cache range */
+       mcrr    p15, 0, r1, r0, c5      /* invalidate I cache range */
+       mcrr    p15, 0, r1, r0, c14     /* clean & invalidate D cache range */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
        RET
 END(armv6_idcache_wbinv_range)