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[src/trunk]: src/sys/arch/evbarm/awin Only look at the ID register if we are ...
details: https://anonhg.NetBSD.org/src/rev/c0bb9663608d
branches: trunk
changeset: 803629:c0bb9663608d
user: matt <matt%NetBSD.org@localhost>
date: Wed Nov 05 17:46:51 2014 +0000
description:
Only look at the ID register if we are configured for multiple SoCs.
Make sure that the ID register is dealt with correctly for BE as well.
diffstat:
sys/arch/evbarm/awin/awin_start.S | 21 +++++++++++++++++++--
1 files changed, 19 insertions(+), 2 deletions(-)
diffs (57 lines):
diff -r 1d9574773882 -r c0bb9663608d sys/arch/evbarm/awin/awin_start.S
--- a/sys/arch/evbarm/awin/awin_start.S Wed Nov 05 17:03:40 2014 +0000
+++ b/sys/arch/evbarm/awin/awin_start.S Wed Nov 05 17:46:51 2014 +0000
@@ -41,7 +41,7 @@
#include <arm/allwinner/awin_reg.h>
#include <evbarm/awin/platform.h>
-RCSID("$NetBSD: awin_start.S,v 1.5 2014/10/30 01:15:30 jmcneill Exp $")
+RCSID("$NetBSD: awin_start.S,v 1.6 2014/11/05 17:46:51 matt Exp $")
#if defined(VERBOSE_INIT_ARM)
#define XPUTC(n) mov r0, n; bl xputc
@@ -151,26 +151,43 @@
// Make sure the cache is flushed out to RAM for the other CPUs
bl _C_LABEL(armv7_dcache_wbinv_all)
+#if defined(ALLWINNER_A20) + defined(ALLWINNER_A31) + defined(ALLWINNER_A80) > 1
// Read SoC ID
movw r5, #:lower16:(AWIN_CORE_PBASE+AWIN_SRAM_OFFSET)
movt r5, #:upper16:(AWIN_CORE_PBASE+AWIN_SRAM_OFFSET)
ldr r1, [r5, #AWIN_SRAM_VER_REG]
- orr r1, r1, AWIN_SRAM_VER_R_EN
+#ifdef __ARMEB__
+ orr r1, r1, #(AWIN_SRAM_VER_R_EN << 8) # it's bit 15
+#else
+ orr r1, r1, #AWIN_SRAM_VER_R_EN
+#endif
str r1, [r5, #AWIN_SRAM_VER_REG]
dsb
ldr r1, [r5, #AWIN_SRAM_VER_REG]
+#ifdef __ARMEB__
+ rev r1, r1
+#endif
lsr r1, r1, #16
+#endif /* ALLWINNER_A20 + ALLWINNER_A31 + ALLWINNER_A80 > 1 */
// MP init based on SoC ID
#if defined(ALLWINNER_A20)
+# if defined(ALLWINNER_A31) || defined(ALLWINNER_A80)
movw r0, #AWIN_SRAM_VER_KEY_A20
cmp r1, r0
bleq a20_mpinit
+# else
+ bl a20_mpinit
+# endif
#endif
#if defined(ALLWINNER_A31)
+# if defined(ALLWINNER_A20) || defined(ALLWINNER_A80)
movw r0, #AWIN_SRAM_VER_KEY_A31
cmp r1, r0
bleq a31_mpinit
+# else
+ bl a31_mpinit
+# endif
#endif
XPUTC2(#62)
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