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[src/trunk]: src/sys/dev/mii Add new file mii/mdio.h which contain IEEE 802.3...



details:   https://anonhg.NetBSD.org/src/rev/1afeaca47e4f
branches:  trunk
changeset: 786101:1afeaca47e4f
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Apr 15 11:48:27 2013 +0000

description:
Add new file mii/mdio.h which contain IEEE 802.3 Clause 45 MDIO
register definitions. From:
 - IEEE 802.3 2009
 - IEEE 802.3at
 - IEEE 802.3av
 - IEEE 802.3az
Currently, only device addresses and register number are written.

diffstat:

 sys/dev/mii/mdio.h |  477 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 477 insertions(+), 0 deletions(-)

diffs (truncated from 481 to 300 lines):

diff -r 683e0220c4e6 -r 1afeaca47e4f sys/dev/mii/mdio.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/mii/mdio.h        Mon Apr 15 11:48:27 2013 +0000
@@ -0,0 +1,477 @@
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_MII_MDIO_H_
+#define        _DEV_MII_MDIO_H_
+
+/*
+ * IEEE 802.3 Clause 45 definitions.
+ * From:
+ *     IEEE 802.3 2008
+ *     IEEE 802.3at
+ *     IEEE 802.3av
+ *     IEEE 802.3az
+ */
+
+/*
+ * MDIO Manageable Device addresses.
+ * Table 45-1
+ */
+#define        MDIO_MMD_PMAPMD         1
+#define        MDIO_MMD_WIS            2
+#define        MDIO_MMD_PCS            3
+#define        MDIO_MMD_PHYXS          4
+#define        MDIO_MMD_DTEXS          5
+#define        MDIO_MMD_TC             6
+#define        MDIO_MMD_AN             7
+#define        MDIO_MMD_CL22EXT        29
+#define        MDIO_MMD_VNDSP1         30
+#define        MDIO_MMD_VNDSP2         31
+
+/*
+ * MDIO PMA/PMD registers.
+ * Table 45-3
+ */
+#define MDIO_PMAPMD_CTRL1              0   /* PMA/PMD control 1 */
+#define MDIO_PMAPMD_STAT1              1   /* PMA/PMD status 1 */
+#define MDIO_PMAPMD_DEVID1             2   /* PMA/PMD device identifier 1 */
+#define MDIO_PMAPMD_DEVID2             3   /* PMA/PMD device identifier 2 */
+#define MDIO_PMAPMD_SPEED              4   /* PMA/PMD speed ability */
+#define MDIO_PMAPMD_DEVS1              5   /* PMA/PMD devices in package 1 */
+#define MDIO_PMAPMD_DEVS2              6   /* PMA/PMD devices in package 2 */
+#define MDIO_PMAPMD_CTRL2              7   /* PMA/PMD control 2 */
+#define MDIO_PMAPMD_10GSTAT2           8   /* 10G PMA/PMD status 2 */
+#define MDIO_PMAPMD_10GTXDIS           9   /* 10G PMA/PMD transmit disable */
+#define MDIO_PMAPMD_RXSIGDTCT          10  /* 10G PMD receive signal detect */
+#define MDIO_PMAPMD_EXTABLTY           11  /* 10G PMA/PMD ext. ability reg */
+#define MDIO_PMAPMD_P2MPABLTY          12  /* P2MP ability register(802.3av)*/
+       /* Value 13 is reserved */
+#define MDIO_PMAPMD_PKGID1             14  /* PMA/PMD package identifier 1 */
+#define MDIO_PMAPMD_PKGID2             15  /* PMA/PMD package identifier 2 */
+       /* Values 16 to 29 are reserved */
+#define MDIO_PMAPMD_10P2BCTRL          30  /* 10P/2B PMA/PMD control */
+#define MDIO_PMAPMD_10P2BSTAT          31  /* 10P/2B PMA/PMD status */
+#define MDIO_PMAPMD_10P2BLPCTRL                32  /* 10P/2B link partner PMA/D ctrl*/
+#define MDIO_PMAPMD_10P2BLPSTAT                33  /* 10P/2B link partner PMA/D stat*/
+       /* Values 34 to 35 are reserved */
+#define MDIO_PMAPMD_10P2BLLOSCNT       36  /* 10P/2B link loss counter */
+#define MDIO_PMAPMD_10P2BRXSNMGN       37  /* 10P/2B RX SNR margin */
+#define MDIO_PMAPMD_10P2BLPRXSNMG      38  /* 10P/2B link partner RX SNR mgn*/
+#define MDIO_PMAPMD_10P2BLINEATTN      39  /* 10P/2B line attenuation */
+#define MDIO_PMAPMD_10P2BLPLINEATTN    40  /* 10P/2B link partner line atten*/
+#define MDIO_PMAPMD_10P2BLQTHRES       41  /* 10P/2B line quality thresholds*/
+#define MDIO_PMAPMD_10P2BLPLQLTHRES    42  /* 10P/2B link partner LQ thresh.*/
+#define MDIO_PMAPMD_10PFECCOERRS       43  /* 10P FEC correctable errors cnt*/
+#define MDIO_PMAPMD_10PFECUNCOERRS     44  /* 10P FEC uncorrectable err cnt*/
+#define MDIO_PMAPMD_10PLPFECCOERRS     45  /* 10P LP FEC correctable err cnt*/
+#define MDIO_PMAPMD_10PLPFECUNCOERRS   46  /* 10P LP FEC uncorrectable errcn*/
+#define MDIO_PMAPMD_10PELECLENGTH      47  /* 10P electrical length */
+#define MDIO_PMAPMD_10PLPELECLENGTH    48  /* 10P LP electrical length */
+#define MDIO_PMAPMD_10PGENCONFIG       49  /* 10P PMA/PMD general config. */
+#define MDIO_PMAPMD_10PPSDCONFIG       50  /* 10P PSD configuration */
+#define MDIO_PMAPMD_10PDSDRCONF1       51  /* 10P downstream data rate cnf1 */
+#define MDIO_PMAPMD_10PDSDRCONF2       52  /* 10P downstream data rate cnf2 */
+#define MDIO_PMAPMD_10PDSRSCONF                53  /* 10P downstream ReedSolomon cnf*/
+#define MDIO_PMAPMD_10PUSDR1           54  /* 10P upstream data rate cnf1 */
+#define MDIO_PMAPMD_10PUSDR2           55  /* 10P upstream data rate cnf2 */
+#define MDIO_PMAPMD_10PUSRSCONF                56  /* 10P upnstream ReedSolomon cnf */
+#define MDIO_PMAPMD_10PTONEGROUP1      57  /* 10P tone group 1 */
+#define MDIO_PMAPMD_10PTONEGROUP2      58  /* 10P tone group 2 */
+#define MDIO_PMAPMD_10PTONEPARAM1      59  /* 10P tone parameter 1 */
+#define MDIO_PMAPMD_10PTONEPARAM2      60  /* 10P tone parameter 2 */
+#define MDIO_PMAPMD_10PTONEPARAM3      61  /* 10P tone parameter 3 */
+#define MDIO_PMAPMD_10PTONEPARAM4      62  /* 10P tone parameter 4 */
+#define MDIO_PMAPMD_10PTONEPARAM5      63  /* 10P tone parameter 5 */
+#define MDIO_PMAPMD_10PTONECTLACTN     64  /* 10P tone control action */
+#define MDIO_PMAPMD_10PTONESTAT1       65  /* 10P tone status 1 */
+#define MDIO_PMAPMD_10PTONESTAT2       66  /* 10P tone status 2 */
+#define MDIO_PMAPMD_10PTONESTAT3       67  /* 10P tone status 3 */
+#define MDIO_PMAPMD_10POUTINDICAT      68  /* 10P outgoing indicatior bits */
+#define MDIO_PMAPMD_10PININDICAT       69  /* 10P incoming indicatior bits */
+#define MDIO_PMAPMD_10PCYCLICEXTCNF    70  /* 10P cyclic extension config. */
+#define MDIO_PMAPMD_10PATTAINDSDR      71  /* 10P attainable downstream DR */
+       /* Values 72 to 79 are reserved */
+#define MDIO_PMAPMD_2BGENPARAM         80  /* 2B general parameter */
+#define MDIO_PMAPMD_2BPMDPARAM1                81  /* 2B PMD parameter 1 */
+#define MDIO_PMAPMD_2BPMDPARAM2                82  /* 2B PMD parameter 2 */
+#define MDIO_PMAPMD_2BPMDPARAM3                83  /* 2B PMD parameter 3 */
+#define MDIO_PMAPMD_2BPMDPARAM4                84  /* 2B PMD parameter 4 */
+#define MDIO_PMAPMD_2BPMDPARAM5                85  /* 2B PMD parameter 5 */
+#define MDIO_PMAPMD_2BPMDPARAM6                86  /* 2B PMD parameter 6 */
+#define MDIO_PMAPMD_2BPMDPARAM7                87  /* 2B PMD parameter 7 */
+#define MDIO_PMAPMD_2BPMDPARAM8                88  /* 2B PMD parameter 8 */
+#define MDIO_PMAPMD_2BCODEVIOERRCNT    89  /* 2B code violation errors cnt. */
+#define MDIO_PMAPMD_2BLPCODEVIOERR     90  /* 2B LP code violation errors */
+#define MDIO_PMAPMD_2BERRSECCNT                91  /* 2B errored seconds counter */
+#define MDIO_PMAPMD_2BLPERRSEC         92  /* 2B LP errored seconds */
+#define MDIO_PMAPMD_2BSEVERRSECCNT     93  /* 2B severely errored seconds cn*/
+#define MDIO_PMAPMD_2BLPSEVERRSECCNT   94 /* 2B LP severely errored secs cn*/
+#define MDIO_PMAPMD_2BLOSWCNT          95  /* 2B LOSW counter */
+#define MDIO_PMAPMD_2BLPLOSW           96  /* 2B LP LOSW */
+#define MDIO_PMAPMD_2BUNAVSECCNT       97  /* 2B unavailable seconds counter*/
+#define MDIO_PMAPMD_2BLPUNAVSECCNT     98  /* 2B LP unavailable seconds cnt */
+#define MDIO_PMAPMD_2BSTATDEFECT       99  /* 2B state defects */
+#define MDIO_PMAPMD_2BLPSTATDEFECT     100 /* 2B LP state defects */
+#define MDIO_PMAPMD_2BNEGOCONSTEL      101 /* 2B negotiated constellation */
+#define MDIO_PMAPMD_2BEXTPMDPARAM1     102 /* 2B extended PMD parameters 1 */
+#define MDIO_PMAPMD_2BEXTPMDPARAM2     103 /* 2B extended PMD parameters 2 */
+#define MDIO_PMAPMD_2BEXTPMDPARAM3     104 /* 2B extended PMD parameters 3 */
+#define MDIO_PMAPMD_2BEXTPMDPARAM4     105 /* 2B extended PMD parameters 4 */
+#define MDIO_PMAPMD_2BEXTPMDPARAM5     106 /* 2B extended PMD parameters 5 */
+#define MDIO_PMAPMD_2BEXTPMDPARAM6     107 /* 2B extended PMD parameters 6 */
+#define MDIO_PMAPMD_2BEXTPMDPARAM7     108 /* 2B extended PMD parameters 7 */
+#define MDIO_PMAPMD_2BEXTPMDPARAM8     109 /* 2B extended PMD parameters 8 */
+       /* Values 110 to 128 are reserved */
+#define MDIO_PMAPMD_10GTSTAT           129 /* 10GBASE-T status */
+#define MDIO_PMAPMD_10GTPASWPOLAR      130 /* 10G-T pair swap & polarity */
+#define MDIO_PMAPMD_10GTTXPWBOSHRCH    131 /* 10G-T PWR backoff&PHY shrt rch*/
+#define MDIO_PMAPMD_10GTTSTMODE                132 /* 10G-T test mode */
+#define MDIO_PMAPMD_10GTSNROMARGA      133 /* 10G-T SNR operating margin chA*/
+#define MDIO_PMAPMD_10GTSNROMARGB      134 /* 10G-T SNR operating margin chB*/
+#define MDIO_PMAPMD_10GTSNROMARGC      135 /* 10G-T SNR operating margin chC*/
+#define MDIO_PMAPMD_10GTSNROMARGD      136 /* 10G-T SNR operating margin chD*/
+#define MDIO_PMAPMD_10GTMINMARGA       137 /* 10G-T minimum margin ch. A */
+#define MDIO_PMAPMD_10GTMINMARGB       138 /* 10G-T minimum margin ch. B */
+#define MDIO_PMAPMD_10GTMINMARGC       139 /* 10G-T minimum margin ch. C */
+#define MDIO_PMAPMD_10GTMINMARGD       140 /* 10G-T minimum margin ch. D */
+#define MDIO_PMAPMD_10GTSIGPWRA                141 /* 10G-T RX signal power ch. A */
+#define MDIO_PMAPMD_10GTSIGPWRB                142 /* 10G-T RX signal power ch. B */
+#define MDIO_PMAPMD_10GTSIGPWRC                143 /* 10G-T RX signal power ch. C */
+#define MDIO_PMAPMD_10GTSIGPWRD                144 /* 10G-T RX signal power ch. D */
+#define MDIO_PMAPMD_10GTSKEWDLY1       145 /* 10G-T skew delay 1 */
+#define MDIO_PMAPMD_10GTSKEWDLY2       146 /* 10G-T skew delay 2 */
+#define MDIO_PMAPMD_10GTFSTRETSTATCTRL 147 /* 10G-T fast retrain stat&ctrl */
+/* Values 148 to 149 are reserved */
+#define MDIO_PMAPMD_10GKRPMDCTRL       150 /* 10G-KR PMD control */
+#define MDIO_PMAPMD_10GKRPMDSTAT       151 /* 10G-KR PMD status */
+#define MDIO_PMAPMD_10GKRLPCOEFUPD     152 /* 10G-KR LP coefficient update */
+#define MDIO_PMAPMD_10GKRLPSTATRPT     153 /* 10G-KR LP status report */
+#define MDIO_PMAPMD_10GKRLDCOEFFUPD    154 /* 10G-KR LD coefficient update */
+#define MDIO_PMAPMD_10GKRLDSTATRPT     155 /* 10G-KR LD status report */
+       /* Values 156 to 159 are reserved */
+#define MDIO_PMAPMD_10GKXCTRL          160 /* 10G-KX control */
+#define MDIO_PMAPMD_10GKXSTAT          161 /* 10G-KX status */
+       /* Values 162 to 169 are reserved */
+#define MDIO_PMAPMD_10GRFECABLTY       170 /* 10G-R FEC ability */
+#define MDIO_PMAPMD_10GRFECCTRL                171 /* 10G-R FEC control */
+#define MDIO_PMAPMD_10GRFECCOBLCNT1    172 /* 10G-R FEC corrected blks cnt1 */
+#define MDIO_PMAPMD_10GRFECCOBLCNT2    173 /* 10G-R FEC corrected blks cnt2 */
+#define MDIO_PMAPMD_10GRFECUNCOBLCNT1  174 /* 10G-R FEC uncorrect blks cnt1 */
+#define MDIO_PMAPMD_10GRFECUNCOBLCNT2  175 /* 10G-R FEC uncorrect blks cnt2 */
+       /* Values 176 to 32767 are reserved */
+       /* Values 32768 to 65535 are vendor specific */
+
+/*
+ * MDIO WIS registers.
+ * Table 45-65
+ */
+#define        MDIO_WIS_CTRL1          0       /* WIS control 1 */
+#define        MDIO_WIS_STAT1          1       /* WIS status 1 */
+#define        MDIO_WIS_DEVID1         2       /* WIS device identifier 1 */
+#define        MDIO_WIS_DEVID2         3       /* WIS device identifier 2 */
+#define        MDIO_WIS_SPEED          4       /* WIS speed ability */
+#define        MDIO_WIS_DEVS1          5       /* WIS devices in package 1 */
+#define        MDIO_WIS_DEVS2          6       /* WIS devices in package 2 */
+#define        MDIO_WIS_10GCTRL2       7       /* 10G WIS control 2 */
+#define        MDIO_WIS_10GSTAT2       8       /* 10G WIS status 2 */
+#define        MDIO_WIS_10GTSTERRCNT   9       /* 10G WIS test-pattern error counter*/
+       /* Values 10 to 13 are reserved */
+#define        MDIO_WIS_PKGID1         14      /* WIS package identifier 1 */
+#define        MDIO_WIS_PKGID2         15      /* WIS package identifier 2 */
+       /* Values 16 to 32 are reserved */
+#define        MDIO_WIS_10GSTAT3       33      /* 10G WIS status 3 */
+       /* Values 34 to 36 are reserved */
+#define        MDIO_WIS_FARENDPBERRCNT 37      /* WIS far end path block error count*/
+       /* Value 38 is reserved */
+#define        MDIO_WIS_J1XMIT1        39      /* 10G WIS J1 transmit 1 */
+#define        MDIO_WIS_J1XMIT2        40      /* 10G WIS J1 transmit 2 */
+#define        MDIO_WIS_J1XMIT3        41      /* 10G WIS J1 transmit 3 */
+#define        MDIO_WIS_J1XMIT4        42      /* 10G WIS J1 transmit 4 */
+#define        MDIO_WIS_J1XMIT5        43      /* 10G WIS J1 transmit 5 */
+#define        MDIO_WIS_J1XMIT6        44      /* 10G WIS J1 transmit 6 */
+#define        MDIO_WIS_J1XMIT7        45      /* 10G WIS J1 transmit 7 */
+#define        MDIO_WIS_J1XMIT8        46      /* 10G WIS J1 transmit 8 */
+#define        MDIO_WIS_J1RECV1        47      /* 10G WIS J1 receive 1 */
+#define        MDIO_WIS_J1RECV2        48      /* 10G WIS J1 receive 2 */
+#define        MDIO_WIS_J1RECV3        49      /* 10G WIS J1 receive 3 */
+#define        MDIO_WIS_J1RECV4        50      /* 10G WIS J1 receive 4 */
+#define        MDIO_WIS_J1RECV5        51      /* 10G WIS J1 receive 5 */
+#define        MDIO_WIS_J1RECV6        52      /* 10G WIS J1 receive 6 */
+#define        MDIO_WIS_J1RECV7        53      /* 10G WIS J1 receive 7 */
+#define        MDIO_WIS_J1RECV8        54      /* 10G WIS J1 receive 8 */
+#define        MDIO_WIS_FARENDLBIPERR1 55      /* 10G WIS far end line BIP errors 1 */
+#define        MDIO_WIS_FARENDLBIPERR2 56      /* 10G WIS far end line BIP errors 2 */
+#define        MDIO_WIS_LBIPERR1       57      /* 10G WIS line BIP errors 1 */
+#define        MDIO_WIS_LBIPERR2       58      /* 10G WIS line BIP errors 2 */
+#define        MDIO_WIS_PBERRCNT       59      /* 10G WIS path block error count */
+#define        MDIO_WIS_SECBIPERRCNT   60      /* 10G WIS section BIP error count */
+       /* Values 61 to 63 are reserved */
+#define        MDIO_WIS_J0XMIT1        64      /* 10G WIS J0 transmit 1 */
+#define        MDIO_WIS_J0XMIT2        65      /* 10G WIS J0 transmit 2 */
+#define        MDIO_WIS_J0XMIT3        66      /* 10G WIS J0 transmit 3 */
+#define        MDIO_WIS_J0XMIT4        67      /* 10G WIS J0 transmit 4 */
+#define        MDIO_WIS_J0XMIT5        68      /* 10G WIS J0 transmit 5 */
+#define        MDIO_WIS_J0XMIT6        69      /* 10G WIS J0 transmit 6 */
+#define        MDIO_WIS_J0XMIT7        70      /* 10G WIS J0 transmit 7 */
+#define        MDIO_WIS_J0XMIT8        71      /* 10G WIS J0 transmit 8 */
+#define        MDIO_WIS_J0RECV1        72      /* 10G WIS J0 receive 1 */
+#define        MDIO_WIS_J0RECV2        73      /* 10G WIS J0 receive 2 */
+#define        MDIO_WIS_J0RECV3        74      /* 10G WIS J0 receive 3 */
+#define        MDIO_WIS_J0RECV4        75      /* 10G WIS J0 receive 4 */
+#define        MDIO_WIS_J0RECV5        76      /* 10G WIS J0 receive 5 */
+#define        MDIO_WIS_J0RECV6        77      /* 10G WIS J0 receive 6 */
+#define        MDIO_WIS_J0RECV7        78      /* 10G WIS J0 receive 7 */
+#define        MDIO_WIS_J0RECV8        79      /* 10G WIS J0 receive 8 */
+       /* Values 80 to 32767 are reserved */
+       /* Values 32768 to 65535 are vendor specific */
+
+/*
+ * MDIO PCS registers.
+ * Table 45-82
+ */
+#define        MDIO_PCS_CTRL1          0       /* PCS control 1 */
+#define        MDIO_PCS_STAT1          1       /* PCS status 1 */
+#define        MDIO_PCS_DEVID1         2       /* PCS device identifier 1 */
+#define        MDIO_PCS_DEVID2         3       /* PCS device identifier 2 */
+#define        MDIO_PCS_SPEED          4       /* PCS speed ability */
+#define        MDIO_PCS_DEVS1          5       /* PCS devices in package 1 */
+#define        MDIO_PCS_DEVS2          6       /* PCS devices in package 2 */
+#define        MDIO_PCS_10GCTRL2       7       /* 10G PCS control 2 */
+#define        MDIO_PCS_10GSTAT2       8       /* 10G PCS status 2 */
+       /* Values 9 to 13 are reserved */
+#define        MDIO_PCS_PKGID1         14      /* PCS package identifier 1 */
+#define        MDIO_PCS_PKGID2         15      /* PCS package identifier 2 */
+       /* Values 16 to 19 are reserved */
+#define        MDIO_PCS_EEECAP         20      /* EEE capability register (802.3az) */
+       /* Value 21 is reserved */
+#define        MDIO_PCS_EEEWKERRCNT    22      /* EEE wake error counter (802.3az) */
+       /* Value 23 is reserved */
+#define        MDIO_PCS_10GXSTAT       24      /* 10G-X PCS status */
+#define        MDIO_PCS_10GXSTSCTRL    25      /* 10G-X PCS test control */
+       /* Values 26 to 31 are reserved */
+#define        MDIO_PCS_10GRTSTAT1     32      /* 10G-R & 10G-T PCS status 1 */
+#define        MDIO_PCS_10GRTSTAT2     33      /* 10G-R & 10G-T PCS status 2 */
+#define        MDIO_PCS_10GRTPSEEDA1   34      /* 10G-R PCS test pattern seed A1 */
+#define        MDIO_PCS_10GRTPSEEDA2   35      /* 10G-R PCS test pattern seed A2 */
+#define        MDIO_PCS_10GRTPSEEDA3   36      /* 10G-R PCS test pattern seed A3 */
+#define        MDIO_PCS_10GRTPSEEDA4   37      /* 10G-R PCS test pattern seed A4 */
+#define        MDIO_PCS_10GRTPSEEDB1   38      /* 10G-R PCS test pattern seed B1 */
+#define        MDIO_PCS_10GRTPSEEDB2   39      /* 10G-R PCS test pattern seed B2 */
+#define        MDIO_PCS_10GRTPSEEDB3   40      /* 10G-R PCS test pattern seed B3 */
+#define        MDIO_PCS_10GRTPSEEDB4   41      /* 10G-R PCS test pattern seed B4 */
+#define        MDIO_PCS_10GRTPCTRL     42      /* 10G-R PCS test pattern control */
+#define        MDIO_PCS_10GRTPERRCNT   43      /* 10G-R PCS test pattern err counter*/
+       /* Values 44 to 59 are reserved */
+#define        MDIO_PCS_10P2BCAP       60      /* 10P/2B capability */
+#define        MDIO_PCS_10P2BCTRL      61      /* 10P/2B PCS control register */
+#define        MDIO_PCS_10P2BPMEAVAIL1 62      /* 10P/2B PME available 1 */
+#define        MDIO_PCS_10P2BPMEAVAIL2 63      /* 10P/2B PME available 2 */
+#define        MDIO_PCS_10P2BPMEAGGRG1 64      /* 10P/2B PME aggregate 1 */
+#define        MDIO_PCS_10P2BPMEAGGRG2 65      /* 10P/2B PME aggregate 2 */



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