[src/trunk]: src/sys/arch/arm/arm32 Plug support for PJ4B into our ARM CPU in...

[rkujawa <rkujawa%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ce10e544aab1
branches:  trunk
changeset: 786894:ce10e544aab1
user:      rkujawa <rkujawa%NetBSD.org@localhost>
date:      Sun May 19 15:42:23 2013 +0000

description:
Plug support for PJ4B into our ARM CPU infrastructure.

Obtained from Marvell, Semihalf.

diffstat:

 sys/arch/arm/arm32/cpu.c |  52 +++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 49 insertions(+), 3 deletions(-)

diffs (122 lines):

diff -r eb8ca4530e04 -r ce10e544aab1 sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c  Sun May 19 15:37:06 2013 +0000
+++ b/sys/arch/arm/arm32/cpu.c  Sun May 19 15:42:23 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.93 2013/02/03 15:57:23 matt Exp $    */
+/*     $NetBSD: cpu.c,v 1.94 2013/05/19 15:42:23 rkujawa Exp $ */
 
 /*
  * Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
 
 #include <sys/param.h>
 
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.93 2013/02/03 15:57:23 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.94 2013/05/19 15:42:23 rkujawa Exp $");
 
 #include <sys/systm.h>
 #include <sys/conf.h>
@@ -74,6 +74,7 @@
 void identify_arm_cpu(device_t dv, struct cpu_info *);
 void identify_cortex_caches(device_t dv);
 void identify_features(device_t dv);
+u_int cpu_pfr(int num);
 
 /*
  * Identify the master (boot) CPU
@@ -227,6 +228,7 @@
        CPU_CLASS_ARM11J,
        CPU_CLASS_ARMV4,
        CPU_CLASS_CORTEX,
+       CPU_CLASS_PJ4B,
 };
 
 static const char * const generic_steppings[16] = {
@@ -487,6 +489,22 @@
        { CPU_ID_CORTEXA15R3,   CPU_CLASS_CORTEX,       "Cortex-A15 r3",
          pN_steppings, "7A" },
 
+       { CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B,      "Sheeva 88SV581x",
+         generic_steppings },
+       { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_PJ4B,    "Sheeva 88SV581x",
+         generic_steppings },
+       { CPU_ID_MV88SV581X_V7, CPU_CLASS_PJ4B,      "Sheeva 88SV581x",
+         generic_steppings },
+       { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_PJ4B,    "Sheeva 88SV581x",
+         generic_steppings },
+       { CPU_ID_MV88SV584X_V6, CPU_CLASS_PJ4B,      "Sheeva 88SV584x",
+         generic_steppings },
+       { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_PJ4B,    "Sheeva 88SV584x",
+         generic_steppings },
+       { CPU_ID_MV88SV584X_V7, CPU_CLASS_PJ4B,      "Sheeva 88SV584x",
+         generic_steppings },
+
+
        { 0, CPU_CLASS_NONE, NULL, NULL, "" }
 };
 
@@ -514,6 +532,7 @@
        [CPU_CLASS_ARM11J] =    { "ARM11J",     "CPU_ARM11" },
        [CPU_CLASS_ARMV4] =     { "ARMv4",      "CPU_ARMV4" },
        [CPU_CLASS_CORTEX] =    { "Cortex",     "CPU_CORTEX" },
+       [CPU_CLASS_PJ4B] =      { "Marvell",    "CPU_PJ4B" },
 };
 
 /*
@@ -560,6 +579,29 @@
        }
 }
 
+u_int cpu_pfr(int num)
+{
+       u_int feat;
+
+       switch (num) {
+       case 0:
+               __asm __volatile("mrc p15, 0, %0, c0, c1, 0"
+                   : "=r" (feat));
+               break;
+       case 1:
+               __asm __volatile("mrc p15, 0, %0, c0, c1, 1"
+                  : "=r" (feat));
+               break;
+       default:
+               panic("Processor Feature Register %d not implemented", num);
+               break;
+       }
+
+       return (feat);
+}
+
+
+
 void
 identify_arm_cpu(device_t dv, struct cpu_info *ci)
 {
@@ -627,6 +669,7 @@
        case CPU_CLASS_ARM11J:
        case CPU_CLASS_ARMV4:
        case CPU_CLASS_CORTEX:
+       case CPU_CLASS_PJ4B:
                if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
                        aprint_normal(" DC disabled");
                else
@@ -654,7 +697,7 @@
 
        aprint_normal("\n");
 
-       if (CPU_ID_CORTEX_P(cpuid) || CPU_ID_ARM11_P(cpuid)) {
+       if (CPU_ID_CORTEX_P(cpuid) || CPU_ID_ARM11_P(cpuid) || CPU_ID_MV88SV58XX_P(cpuid)) {
                identify_features(dv);
        }
 
@@ -714,6 +757,9 @@
 #if defined(CPU_CORTEX)
        case CPU_CLASS_CORTEX:
 #endif
+#if defined(CPU_PJ4B)
+       case CPU_CLASS_PJ4B:
+#endif
 #if defined(CPU_FA526)
        case CPU_CLASS_ARMV4:
 #endif