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[src/trunk]: src/sys/arch/arm/sunxi Add driver for sun4i (A10) and sun7i (A20...



details:   https://anonhg.NetBSD.org/src/rev/8905b5c060ab
branches:  trunk
changeset: 826932:8905b5c060ab
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Oct 06 21:09:21 2017 +0000

description:
Add driver for sun4i (A10) and sun7i (A20) clock controller.

diffstat:

 sys/arch/arm/sunxi/files.sunxi      |    7 +-
 sys/arch/arm/sunxi/sun4i_a10_ccu.c  |  408 ++++++++++++++++++++++++++++++++++++
 sys/arch/arm/sunxi/sun4i_a10_ccu.h  |  221 +++++++++++++++++++
 sys/arch/arm/sunxi/sun7i_a20_ccu.h  |   40 +++
 sys/arch/arm/sunxi/sunxi_ccu.h      |   11 +-
 sys/arch/arm/sunxi/sunxi_ccu_nkmp.c |    7 +-
 6 files changed, 686 insertions(+), 8 deletions(-)

diffs (truncated from 755 to 300 lines):

diff -r 72d9646178cb -r 8905b5c060ab sys/arch/arm/sunxi/files.sunxi
--- a/sys/arch/arm/sunxi/files.sunxi    Fri Oct 06 20:26:51 2017 +0000
+++ b/sys/arch/arm/sunxi/files.sunxi    Fri Oct 06 21:09:21 2017 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.sunxi,v 1.26 2017/10/05 01:30:26 jmcneill Exp $
+#      $NetBSD: files.sunxi,v 1.27 2017/10/06 21:09:21 jmcneill Exp $
 #
 # Configuration info for Allwinner sunxi family SoCs
 #
@@ -28,6 +28,11 @@
 file   arch/arm/sunxi/sunxi_ccu_phase.c        sunxi_ccu
 file   arch/arm/sunxi/sunxi_ccu_prediv.c       sunxi_ccu
 
+# CCU (A10/A20)
+device sun4ia10ccu: sunxi_ccu
+attach sun4ia10ccu at fdt with sunxi_a10_ccu
+file   arch/arm/sunxi/sun4i_a10_ccu.c          sunxi_a10_ccu
+
 # CCU (A13)
 device sun5ia13ccu: sunxi_ccu
 attach sun5ia13ccu at fdt with sunxi_a13_ccu
diff -r 72d9646178cb -r 8905b5c060ab sys/arch/arm/sunxi/sun4i_a10_ccu.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun4i_a10_ccu.c        Fri Oct 06 21:09:21 2017 +0000
@@ -0,0 +1,408 @@
+/* $NetBSD: sun4i_a10_ccu.c,v 1.1 2017/10/06 21:09:21 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.1 2017/10/06 21:09:21 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun4i_a10_ccu.h>
+#include <arm/sunxi/sun7i_a20_ccu.h>
+
+#define        PLL1_CFG_REG            0x000
+#define        PLL2_CFG_REG            0x008
+#define        PLL6_CFG_REG            0x028
+#define        OSC24M_CFG_REG          0x050
+#define        CPU_AHB_APB0_CFG_REG    0x054
+#define        APB1_CLK_DIV_REG        0x058
+#define        AHB_GATING_REG0         0x060
+#define        AHB_GATING_REG1         0x064
+#define        APB0_GATING_REG         0x068
+#define        APB1_GATING_REG         0x06c
+#define        SD0_SCLK_CFG_REG        0x088
+#define        SD1_SCLK_CFG_REG        0x08c
+#define        SD2_SCLK_CFG_REG        0x090
+#define        SD3_SCLK_CFG_REG        0x094
+#define        USBPHY_CFG_REG          0x0cc
+#define        BE_CFG_REG              0x104
+#define        FE_CFG_REG              0x10c
+#define        CSI_CFG_REG             0x134
+#define        VE_CFG_REG              0x13c
+#define        AUDIO_CODEC_SCLK_CFG_REG 0x140
+#define        MALI_CLOCK_CFG_REG      0x154
+#define        IEP_SCLK_CFG_REG        0x160
+
+static int sun4i_a10_ccu_match(device_t, cfdata_t, void *);
+static void sun4i_a10_ccu_attach(device_t, device_t, void *);
+
+enum sun4i_a10_ccu_type {
+       CCU_A10 = 1,
+       CCU_A20,
+};
+
+static const struct of_compat_data compat_data[] = {
+       { "allwinner,sun4i-a10-ccu",    CCU_A10 },
+       { "allwinner,sun7i-a20-ccu",    CCU_A20 },
+       { NULL }
+};
+
+CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc),
+       sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = {
+       SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0),
+       SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1),
+       SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2),
+};
+
+static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" };
+static const char *axi_parents[] = { "cpu" };
+static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" };
+static const char *apb0_parents[] = { "ahb" };
+static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" };
+static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" };
+
+static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = {
+       { 24576000, 86, 0, 21, 3 },
+       { 0 }
+};
+
+static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = {
+       SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc",
+           OSC24M_CFG_REG, 0),
+
+       SUNXI_CCU_NKMP(A10_CLK_PLL_CORE, "pll_core", "osc24m",
+           PLL1_CFG_REG,               /* reg */
+           __BITS(12,8),               /* n */
+           __BITS(5,4),                /* k */
+           __BITS(1,0),                /* m */
+           __BITS(17,16),              /* p */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT |
+           SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE),
+
+       SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m",
+           PLL2_CFG_REG,               /* reg */
+           __BITS(14,8),               /* n */
+           0,                          /* k */
+           __BITS(4,0),                /* m */
+           __BITS(29,26),              /* p */
+           __BIT(31),                  /* enable */
+           0,                          /* lock */
+           sun4i_a10_ac_dig_table,     /* table */
+           0),
+
+       SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m",
+           PLL6_CFG_REG,               /* reg */
+           __BITS(12,8),               /* n */
+           __BITS(5,4),                /* k */
+           0,                          /* m */
+           0,                          /* p */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NKMP_FACTOR_N_EXACT),
+
+       SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base",
+           2, 1),
+
+       SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base",
+           PLL6_CFG_REG,               /* reg */
+           0,                          /* n */
+           0,                          /* k */
+           __BITS(1,0),                /* m */
+           0,                          /* p */
+           __BIT(14),                  /* enable */
+           0),
+
+       SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents,
+           CPU_AHB_APB0_CFG_REG,       /* reg */
+           0,                          /* div */
+           __BITS(17,16),              /* sel */
+           0),
+
+       SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents,
+           CPU_AHB_APB0_CFG_REG,       /* reg */
+           __BITS(1,0),                /* div */
+           0,                          /* sel */
+           0),
+
+       SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents,
+           CPU_AHB_APB0_CFG_REG,       /* reg */
+           __BITS(5,4),                /* div */
+           __BITS(7,6),                /* sel */
+           SUNXI_CCU_DIV_POWER_OF_TWO),
+
+       SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents,
+           CPU_AHB_APB0_CFG_REG,       /* reg */
+           __BITS(9,8),                /* div */
+           0,                          /* sel */
+           SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO),
+
+       SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents,
+           APB1_CLK_DIV_REG,           /* reg */
+           __BITS(17,16),              /* n */
+           __BITS(4,0),                /* m */
+           __BITS(25,24),              /* sel */
+           0,                          /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+
+       SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents,
+           SD0_SCLK_CFG_REG,           /* reg */
+           __BITS(17,16),              /* n */
+           __BITS(3,0),                /* m */
+           __BITS(25,24),              /* sel */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+       SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents,
+           SD1_SCLK_CFG_REG,           /* reg */
+           __BITS(17,16),              /* n */
+           __BITS(3,0),                /* m */
+           __BITS(25,24),              /* sel */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+       SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents,
+           SD2_SCLK_CFG_REG,           /* reg */
+           __BITS(17,16),              /* n */
+           __BITS(3,0),                /* m */
+           __BITS(25,24),              /* sel */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+       SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents,
+           SD3_SCLK_CFG_REG,           /* reg */
+           __BITS(17,16),              /* n */
+           __BITS(3,0),                /* m */
+           __BITS(25,24),              /* sel */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+
+       /* AHB_GATING_REG0 */
+       SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb",
+           AHB_GATING_REG0, 0),
+       SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb",
+           AHB_GATING_REG0, 1),
+       SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb",
+           AHB_GATING_REG0, 2),
+       SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb",
+           AHB_GATING_REG0, 3),
+       SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb",
+           AHB_GATING_REG0, 4),
+       SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb",
+           AHB_GATING_REG0, 5),
+       SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb",
+           AHB_GATING_REG0, 6),
+       SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb",
+           AHB_GATING_REG0, 7),
+       SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb",
+           AHB_GATING_REG0, 8),
+       SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb",
+           AHB_GATING_REG0, 9),
+       SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb",
+           AHB_GATING_REG0, 10),
+       SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb",
+           AHB_GATING_REG0, 11),
+       SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb",
+           AHB_GATING_REG0, 12),
+       SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb",
+           AHB_GATING_REG0, 13),
+       SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb",
+           AHB_GATING_REG0, 14),
+       SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb",
+           AHB_GATING_REG0, 16),
+       SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb",
+           AHB_GATING_REG0, 17),
+       SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb",
+           AHB_GATING_REG0, 18),
+       SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb",
+           AHB_GATING_REG0, 20),
+       SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb",
+           AHB_GATING_REG0, 21),
+       SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb",
+           AHB_GATING_REG0, 22),
+       SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb",
+           AHB_GATING_REG0, 23),
+       SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb",
+           AHB_GATING_REG0, 25),
+       SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb",
+           AHB_GATING_REG0, 28),
+
+       /* AHB_GATING_REG1. Missing: TVE, HDMI */
+       SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb",
+           AHB_GATING_REG1, 0),
+       SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb",
+           AHB_GATING_REG1, 1),
+       SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb",
+           AHB_GATING_REG1, 2),
+       SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb",
+           AHB_GATING_REG1, 3),
+       SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb",
+           AHB_GATING_REG1, 4),
+       SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb",
+           AHB_GATING_REG1, 5),
+       SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb",
+           AHB_GATING_REG1, 8),
+       SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb",
+           AHB_GATING_REG1, 9),



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