[src/trunk]: src/sys/arch/arm/cortex Update GICD_CTLR reg bit definitions to ...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/3c8c127a29b0
branches:  trunk
changeset: 836954:3c8c127a29b0
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Tue Nov 13 22:25:28 2018 +0000

description:
Update GICD_CTLR reg bit definitions to reflect the layout of the register
when either in non-secure state or for a system that only supports a single
state.

diffstat:

 sys/arch/arm/cortex/gic_reg.h |  8 +++-----
 sys/arch/arm/cortex/gicv3.c   |  6 +++---
 2 files changed, 6 insertions(+), 8 deletions(-)

diffs (49 lines):

diff -r 3821b8dbfe7f -r 3c8c127a29b0 sys/arch/arm/cortex/gic_reg.h
--- a/sys/arch/arm/cortex/gic_reg.h     Tue Nov 13 21:22:37 2018 +0000
+++ b/sys/arch/arm/cortex/gic_reg.h     Tue Nov 13 22:25:28 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: gic_reg.h,v 1.8 2018/11/09 23:36:24 jmcneill Exp $     */
+/*     $NetBSD: gic_reg.h,v 1.9 2018/11/13 22:25:28 jmcneill Exp $     */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -143,10 +143,8 @@
 #define        GICD_CTRL_RWP                   __BIT(31)       // GICv3
 #define        GICD_CTRL_E1NWF                 __BIT(7)        // GICv3
 #define        GICD_CTRL_DS                    __BIT(6)        // GICv3
-#define        GICD_CTRL_ARE_NS                __BIT(5)        // GICv3
-#define        GICD_CTRL_ARE_S                 __BIT(4)        // GICv3
-#define        GICD_CTRL_EnableGrp1S           __BIT(2)        // GICv3
-#define        GICD_CTRL_EnableGrp1NS          __BIT(1)        // GICv3
+#define        GICD_CTRL_ARE_NS                __BIT(4)        // GICv3
+#define        GICD_CTRL_EnableGrp1A           __BIT(1)        // GICv3
 #define        GICD_CTRL_Enable                __BIT(0)
 
 #define        GICD_TYPER_No1N                 __BIT(25)       // GICv3
diff -r 3821b8dbfe7f -r 3c8c127a29b0 sys/arch/arm/cortex/gicv3.c
--- a/sys/arch/arm/cortex/gicv3.c       Tue Nov 13 21:22:37 2018 +0000
+++ b/sys/arch/arm/cortex/gicv3.c       Tue Nov 13 22:25:28 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.8 2018/11/13 10:33:03 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.9 2018/11/13 22:25:28 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -31,7 +31,7 @@
 #define        _INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.8 2018/11/13 10:33:03 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.9 2018/11/13 22:25:28 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/kernel.h>
@@ -245,7 +245,7 @@
                ;
 
        /* Enable Affinity routing and G1NS interrupts */
-       gicd_ctrl = GICD_CTRL_EnableGrp1NS | GICD_CTRL_Enable | GICD_CTRL_ARE_NS;
+       gicd_ctrl = GICD_CTRL_EnableGrp1A | GICD_CTRL_Enable | GICD_CTRL_ARE_NS;
        gicd_write_4(sc, GICD_CTRL, gicd_ctrl);
 }