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[src/netbsd-7]: src/sys/arch/arm/omap Pull up following revision(s) (requeste...
details: https://anonhg.NetBSD.org/src/rev/54b176e9fe7e
branches: netbsd-7
changeset: 799214:54b176e9fe7e
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Fri Apr 17 08:44:54 2015 +0000
description:
Pull up following revision(s) (requested by jmcneill in ticket #696):
sys/arch/arm/omap/if_cpsw.c: revision 1.12
sys/arch/arm/omap/if_cpswreg.h: revision 1.5
Disable flow control with CPSW_SS FLOW_CONTROL register (cherry-picked
from FreeBSD driver). Resolves device timeout / watchdog issues for me.
diffstat:
sys/arch/arm/omap/if_cpsw.c | 7 +++++--
sys/arch/arm/omap/if_cpswreg.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diffs (39 lines):
diff -r ddd5649dd852 -r 54b176e9fe7e sys/arch/arm/omap/if_cpsw.c
--- a/sys/arch/arm/omap/if_cpsw.c Thu Apr 16 09:30:35 2015 +0000
+++ b/sys/arch/arm/omap/if_cpsw.c Fri Apr 17 08:44:54 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_cpsw.c,v 1.6 2014/04/09 20:52:14 hans Exp $ */
+/* $NetBSD: if_cpsw.c,v 1.6.2.1 2015/04/17 08:44:54 msaitoh Exp $ */
/*
* Copyright (c) 2013 Jonathan A. Kollasch
@@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.6 2014/04/09 20:52:14 hans Exp $");
+__KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.6.2.1 2015/04/17 08:44:54 msaitoh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -891,6 +891,9 @@
}
sc->sc_rxhead = 0;
+ /* turn off flow control */
+ cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
+
/* align layer 3 header to 32-bit */
cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN);
diff -r ddd5649dd852 -r 54b176e9fe7e sys/arch/arm/omap/if_cpswreg.h
--- a/sys/arch/arm/omap/if_cpswreg.h Thu Apr 16 09:30:35 2015 +0000
+++ b/sys/arch/arm/omap/if_cpswreg.h Fri Apr 17 08:44:54 2015 +0000
@@ -34,6 +34,7 @@
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
+#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
#define CPSW_SS_RGMII_CTL (CPSW_SS_OFFSET + 0x88)
#define CPSW_PORT_OFFSET 0x0100
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