[src/trunk]: src/sys/dev/pci 0x4B657654(BGE_SRAM_FW_MB_MAGIC) == ~0xB49A89AB(...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/395a1fe17b99
branches:  trunk
changeset: 787034:395a1fe17b99
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Thu May 30 05:50:06 2013 +0000

description:
0x4B657654(BGE_SRAM_FW_MB_MAGIC) == ~0xB49A89AB(BGE_SRAM_FW_MB_RESET_MAGIC),
so the same code I added in rev. 1.223 exists in bge_poll_fw(), too. Remove it.

 And then, call bge_poll_fw() before writing BGE_MODE_CTL register like the
latest linux tg3 dirver.

diffstat:

 sys/dev/pci/if_bge.c    |  27 ++++++---------------------
 sys/dev/pci/if_bgereg.h |   5 ++---
 2 files changed, 8 insertions(+), 24 deletions(-)

diffs (78 lines):

diff -r 4a3348400150 -r 395a1fe17b99 sys/dev/pci/if_bge.c
--- a/sys/dev/pci/if_bge.c      Thu May 30 00:07:07 2013 +0000
+++ b/sys/dev/pci/if_bge.c      Thu May 30 05:50:06 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_bge.c,v 1.251 2013/05/29 08:24:06 msaitoh Exp $     */
+/*     $NetBSD: if_bge.c,v 1.252 2013/05/30 05:50:06 msaitoh Exp $     */
 
 /*
  * Copyright (c) 2001 Wind River Systems
@@ -79,7 +79,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.251 2013/05/29 08:24:06 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.252 2013/05/30 05:50:06 msaitoh Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -4149,25 +4149,14 @@
                BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT);
        }
 
+       /* 57XX step 17 */
+       /* Poll until the firmware initialization is complete */
+       bge_poll_fw(sc);
+
        /* 5718 reset step 12, 57XX step 15 and 16 */
        /* Fix up byte swapping */
        CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
 
-       /* 5718 reset step 13, 57XX step 17 */
-       /*
-        * Wait for the bootcode to complete initialization.
-        * See BCM5718 programmer's guide's "step 13, Device reset Procedure,
-        * Section 7". For 57XX, it's optional.
-        */
-       if (BGE_IS_5717_PLUS(sc)) {
-               for (i = 0; i < 1000*1000; i++) {
-                       val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
-                       if (val == BGE_SRAM_FW_MB_RESET_MAGIC)
-                               break;
-                       DELAY(10);
-               }
-       }
-
        /* 57XX step 21 */
        if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) {
                pcireg_t msidata;
@@ -4190,10 +4179,6 @@
 
        bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
 
-       /* 57XX step 17 */
-       /* Poll until the firmware initialization is complete */
-       bge_poll_fw(sc);
-
        /*
         * The 5704 in TBI mode apparently needs some special
         * adjustment to insure the SERDES drive level is set
diff -r 4a3348400150 -r 395a1fe17b99 sys/dev/pci/if_bgereg.h
--- a/sys/dev/pci/if_bgereg.h   Thu May 30 00:07:07 2013 +0000
+++ b/sys/dev/pci/if_bgereg.h   Thu May 30 05:50:06 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_bgereg.h,v 1.79 2013/05/28 05:55:40 msaitoh Exp $   */
+/*     $NetBSD: if_bgereg.h,v 1.80 2013/05/30 05:50:06 msaitoh Exp $   */
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
@@ -2191,8 +2191,7 @@
  * firmware mailbox at 0xB50 in order to prevent the PXE boot
  * code from running.
  */
-#define        BGE_SRAM_FW_MB_MAGIC    0x4B657654
-#define        BGE_SRAM_FW_MB_RESET_MAGIC      0xB49A89AB
+#define        BGE_SRAM_FW_MB_MAGIC    0x4B657654 /* == ~0xB49A89AB */
 
 typedef struct {
        volatile u_int32_t      bge_addr_hi;