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[src/netbsd-7]: src/sys/dev Pull up following revision(s) (requested by msait...
details: https://anonhg.NetBSD.org/src/rev/ece0b5bace54
branches: netbsd-7
changeset: 800047:ece0b5bace54
user: snj <snj%NetBSD.org@localhost>
date: Mon Dec 12 07:18:29 2016 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #1302):
sys/dev/mii/igphyreg.h: revisions 1.7-1.10
sys/dev/mii/ikphyreg.h: revisions 1.3
sys/dev/mii/inbmphyreg.h: revisions 1.4-1.9
sys/dev/mii/mii.h: revisions 1.19-1.20
sys/dev/pci/if_wm.c: revisions 1.390, 1.392-1.395, 1.397, 1.419-1.425, 1.427-1.428, 1.430-1.435, 1.437-1.453 via patch
sys/dev/pci/if_wmreg.: revisions 1.89-1.93 via patch
sys/dev/pci/if_wmvar.h: revisions 1.31-1.32
Update wm(4) up to if_wm.c rev. 1.453 except MSI/MSI-X, multiqueue and
NET_MPSAFE:
- Add I219 support. It's not stable so it's disabled by default.
- wm_gate_hw_phy_config_ich8lan() is for younger than PCH2.
- Drop the host wakeup bit after resetting PHY on PCH and newer
devices.
- Increase delay while toggling LANPHYPC
- Move call of wm_reset() in wm_attach() after setting PHY and NVM
related flags because those flags are used in wm_reset().
- Use mutex for NVM access on ICH8 and newer devices. Same as FreeBSD.
- Rewrite PHY related lock stuff. Almost the same as FreeBSD.
This change will fix a bug that PHY read/write fail on some cases.
- Increase delay in wm_phy_resetisblocked(). Same as FreeBSD.
- Use semaphore in wm_hv_phy_workaround_ich8lan() and
wm_k1_gig_workaround_hv()
- Use wm_gii_mdic_readreg/writereg() in wm_access_phy_wakeup_reg_bm()
because these functions are called with taking lock.
- 82567V_3 is BME1000_E_2(bm). Tested with Advantech AIMB-212 1st
Ethernet port.
- Use wm_gmii_82544_{read,write}reg() on non-82567 ICH8, 9 and 10.
- Remove an 82578 workaround which was for PCH rev < 3. FreeBSD
removed this workaround in r228386.
- Add an 82578 workaround which is for PHY rev < 2. From FreeBSD and
Linux.
- Fix wm(4) input drop packet counter. WMREG_RNBC is incremented when
there is no available buffers in host memory. However, ethernet
controller can receive packets in such case if there is space in
phy's FIFO. That is, ethernet controller drops packet only if there
is no available buffers *and* there is no space in phy's FIFO. So,
the number of dropped packets should be added WMREG_MPC only.
- Use MII_ADDRMASK.
- Define WMPHY_I217, WMPHY_VF and WMPHY_210.
- Use BME1000_PHY_PAGE_SELECT in wm_gmii_bm_{read,write}reg(). This
change has no effect because GG82563_PHY_PAGE_SELECT and
BME1000_PHY_PAGE_SELECT have the same value.
- Fix PHY access on 82567(ICH8 or ICH10), 82574 and 82583:
- Use wm_gmii_bm_{read,write}reg() on 82574 and 82573.
- Issue page select correctly on BM PHYs.
- Fix workaround which did dummy read BM_WUC register. This code was
changed to drop BM_WUC_HOST_WU_BIT of BM_PROT_GEN_CFG register in
FreeBSD r228386. The code was added rev. 1.149, but the location was
not the best.
- wm_gmii_hv_{read/write}reg*(): USE PHY address 1 for some special
registers.
- Add check code for an 82578 workaround. Not completed yet.
- wm_release_hw_control(): Remove extra line. No any effect.
- Add "10/100" into non-gigabit devices' name.
- Call wm_enable_wakeup() in wm_detach() and wm_suspend(). Now wake on
lan works on Thinkpad X61(ICH8).
- Fix wm_access_phy_wakeup_reg_bm(). This change has no effect because
this function is used for WUC register and our driver currenlty
doesn't access to it.
- Call wm_enable_phy_wakeup() on PCH2 and newer, too. Now these devices
can do WOL. Tested with Thinkpad X220(PCH2).
- Set CTRL_MEHE correctly (PCH_{LPT,SPT} only).
- Add three workarounds for PCH_{LPT,SPT}.
- Fix a bug that 8257[56], 82580, I35[04] and I21[01] didn't use
wm_{get,release}_hw_control() correctly.
- Sync wm_smbustopci() with Linux and FreeBSD. This change effects PCH
and newer devices.
- Move the location of wm_smbustopci() call.
- Fix flag check in wm_get_wakeup()
- 8254[17]* and 8257[124] should not set WM_F_ARC_SUBSYS_VALID.
- Add missing WM_T_82541_2 and WM_T_82547_2.
- Fix WOL related setting of the WUC register for other than PCH* in
wm_enable_wakeup(). Tested with 82567V(ICH8) and 82583V.
- Use common MII_ADDRMASK.
- igphy(4): No binary change:
- s/IGPPHY/IGPHY/
- Fix the definition of PLHR_VALID_CHANNEL_*
- Fix the definition of MSE_CHANNEL_*
- Add MII_IGPHY_POWER_MGMT.
- Add some KASSERT.
- Add comment. Modify comment.
- Add debug code.
diffstat:
sys/dev/mii/igphyreg.h | 60 +-
sys/dev/mii/ikphyreg.h | 5 +-
sys/dev/mii/inbmphyreg.h | 37 +-
sys/dev/mii/mii.h | 8 +-
sys/dev/pci/if_wm.c | 1991 +++++++++++++++++++++++++++++++++++----------
sys/dev/pci/if_wmreg.h | 71 +-
sys/dev/pci/if_wmvar.h | 8 +-
7 files changed, 1663 insertions(+), 517 deletions(-)
diffs (truncated from 3836 to 300 lines):
diff -r db73c5fa7f07 -r ece0b5bace54 sys/dev/mii/igphyreg.h
--- a/sys/dev/mii/igphyreg.h Mon Dec 12 07:04:31 2016 +0000
+++ b/sys/dev/mii/igphyreg.h Mon Dec 12 07:18:29 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: igphyreg.h,v 1.6 2010/03/07 09:05:19 msaitoh Exp $ */
+/* $NetBSD: igphyreg.h,v 1.6.36.1 2016/12/12 07:18:29 snj Exp $ */
/*******************************************************************************
@@ -42,14 +42,14 @@
* IGP01E1000 Specific Registers
*/
-/* IGP01E1000 Specific Port Control Register - R/W */
-#define MII_IGPPHY_PORT_CONFIG 0x10 /* PHY specific config register */
-#define PSCR_AUTO_MDIX_PAR_DETECT 0x0010
-#define PSCR_PRE_EN 0x0020
-#define PSCR_SMART_SPEED 0x0080
-#define PSCR_DISABLE_TPLOOPBACK 0x0100
-#define PSCR_DISABLE_JABBER 0x0400
-#define PSCR_DISABLE_TRANSMIT 0x2000
+/* IGP01E1000 Specific Port Config Register - R/W */
+#define MII_IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */
+#define PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
+#define PSCFR_PRE_EN 0x0020
+#define PSCFR_SMART_SPEED 0x0080
+#define PSCFR_DISABLE_TPLOOPBACK 0x0100
+#define PSCFR_DISABLE_JABBER 0x0400
+#define PSCFR_DISABLE_TRANSMIT 0x2000
/* IGP01E1000 Specific Port Status Register - R/O */
#define MII_IGPHY_PORT_STATUS 0x11
@@ -68,7 +68,7 @@
/* IGP01E1000 Specific Port Control Register - R/W */
#define MII_IGPHY_PORT_CTRL 0x12
-#define PSCR_TP_LOOPBACK 0x0001
+#define PSCR_TP_LOOPBACK 0x0010
#define PSCR_CORRECT_NC_SCMBLR 0x0200
#define PSCR_TEN_CRS_SELECT 0x0400
#define PSCR_FLIP_CHIP 0x0800
@@ -77,18 +77,18 @@
/* IGP01E1000 Specific Port Link Health Register */
#define MII_IGPHY_LINK_HEALTH 0x13
-#define PLHR_SS_DOWNGRADE 0x8000
-#define PLHR_GIG_SCRAMBLER_ERROR 0x4000
-#define PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
-#define PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
-#define PLHR_DATA_ERR_1 0x0200 /* LH */
+#define PLHR_VALID_CHANNEL_A 0x0001
+#define PLHR_VALID_CHANNEL_B 0x0002
+#define PLHR_VALID_CHANNEL_C 0x0004
+#define PLHR_VALID_CHANNEL_D 0x0008
+#define PLHR_AUTONEG_ACTIVE 0x0010
+#define PLHR_AUTONEG_FAULT 0x0040
#define PLHR_DATA_ERR_0 0x0100
-#define PLHR_AUTONEG_FAULT 0x0010
-#define PLHR_AUTONEG_ACTIVE 0x0008
-#define PLHR_VALID_CHANNEL_D 0x0004
-#define PLHR_VALID_CHANNEL_C 0x0002
-#define PLHR_VALID_CHANNEL_B 0x0001
-#define PLHR_VALID_CHANNEL_A 0x0000
+#define PLHR_DATA_ERR_1 0x0200 /* LH */
+#define PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
+#define PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
+#define PLHR_GIG_SCRAMBLER_ERROR 0x4000
+#define PLHR_SS_DOWNGRADE 0x8000
/* IGP01E1000 GMII FIFO Register */
#define MII_IGGMII_FIFO 0x14
@@ -97,10 +97,17 @@
/* IGP01E1000 Channel Quality Register */
#define MII_IGPHY_CHANNEL_QUALITY 0x15
-#define MSE_CHANNEL_D 0x000F
-#define MSE_CHANNEL_C 0x00F0
-#define MSE_CHANNEL_B 0x0F00
-#define MSE_CHANNEL_A 0xF000
+#define MSE_CHANNEL_A 0x000F
+#define MSE_CHANNEL_B 0x00F0
+#define MSE_CHANNEL_C 0x0F00
+#define MSE_CHANNEL_D 0xF000
+
+/* IGP01E1000 Power Management */
+#define MII_IGPHY_POWER_MGMT 0x19
+#define PMR_SPD_EN 0x0001
+#define PMR_D0_LPLU 0x0002
+#define PMR_D3_LPLU 0x0004
+#define PMR_DIS_1000 0x0040
#define MII_IGPHY_PAGE_SELECT 0x1F
#define IGPHY_MAXREGADDR 0x1F
@@ -158,9 +165,8 @@
* IGP3 regs
*/
#define IGP3_PAGE_SHIFT 5
-#define IGP3_MAX_REG_ADDRESS 0x1f /* 5 bit address bus (0-0x1f) */
#define IGP3_REG(page, reg) \
- (((page) << IGP3_PAGE_SHIFT) | ((reg) & IGP3_MAX_REG_ADDRESS))
+ (((page) << IGP3_PAGE_SHIFT) | ((reg) & MII_ADDRMASK))
#define IGP3_VR_CTRL IGP3_REG(776, 18)
#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
diff -r db73c5fa7f07 -r ece0b5bace54 sys/dev/mii/ikphyreg.h
--- a/sys/dev/mii/ikphyreg.h Mon Dec 12 07:04:31 2016 +0000
+++ b/sys/dev/mii/ikphyreg.h Mon Dec 12 07:18:29 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ikphyreg.h,v 1.2 2010/11/29 23:04:42 jym Exp $ */
+/* $NetBSD: ikphyreg.h,v 1.2.34.1 2016/12/12 07:18:29 snj Exp $ */
/*******************************************************************************
Copyright (c) 2001-2005, Intel Corporation
All rights reserved.
@@ -41,10 +41,9 @@
*/
#define GG82563_PAGE_SHIFT 5
#define GG82563_REG(page, reg) \
- (((page) << GG82563_PAGE_SHIFT) | ((reg) & GG82563_MAX_REG_ADDRESS))
+ (((page) << GG82563_PAGE_SHIFT) | ((reg) & MII_ADDRMASK))
#define GG82563_MIN_ALT_REG 30
-#define GG82563_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
#define GG82563_MAX_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
diff -r db73c5fa7f07 -r ece0b5bace54 sys/dev/mii/inbmphyreg.h
--- a/sys/dev/mii/inbmphyreg.h Mon Dec 12 07:04:31 2016 +0000
+++ b/sys/dev/mii/inbmphyreg.h Mon Dec 12 07:18:29 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: inbmphyreg.h,v 1.3 2011/05/20 06:06:59 msaitoh Exp $ */
+/* $NetBSD: inbmphyreg.h,v 1.3.30.1 2016/12/12 07:18:29 snj Exp $ */
/*******************************************************************************
Copyright (c) 2001-2005, Intel Corporation
All rights reserved.
@@ -44,16 +44,15 @@
*/
#define BME1000_PAGE_SHIFT 5
#define BME1000_REG(page, reg) \
- (((page) << BME1000_PAGE_SHIFT) | ((reg) & BME1000_MAX_REG_ADDRESS))
+ (((page) << BME1000_PAGE_SHIFT) | ((reg) & MII_ADDRMASK))
-#define BME1000_MAX_REG_ADDRESS 0x1f /* 5 bit address bus (0-0x1f) */
#define BME1000_MAX_MULTI_PAGE_REG 0xf /* Registers equal on all pages */
#define BM_PHY_REG_PAGE(offset) \
((uint16_t)(((offset) >> BME1000_PAGE_SHIFT) & 0xffff))
-#define BM_PHY_REG_NUM(offset) \
- ((uint16_t)((offset) & BME1000_MAX_REG_ADDRESS) \
- | (((offset) >> (21 - BME1000_PAGE_SHIFT)) & ~BME1000_MAX_REG_ADDRESS))
+#define BM_PHY_REG_NUM(offset) \
+ ((uint16_t)((offset) & MII_ADDRMASK) \
+ | (((offset) >> (21 - BME1000_PAGE_SHIFT)) & ~MII_ADDRMASK))
/* BME1000 Specific Registers */
#define BME1000_PHY_SPEC_CTRL BME1000_REG(0, 16) /* PHY Specific Control */
@@ -84,17 +83,25 @@
#define I82577_ADDR_REG 16
#define I82577_CFG_REG 22
+#define HV_INTC_FC_PAGE_START 768
+#define BM_PORT_CTRL_PAGE 769
+
#define HV_OEM_BITS BME1000_REG(0, 25)
#define HV_OEM_BITS_LPLU (1 << 2)
#define HV_OEM_BITS_A1KDIS (1 << 6)
#define HV_OEM_BITS_ANEGNOW (1 << 10)
-#define HV_INTC_FC_PAGE_START 768
-#define BM_PORT_CTRL_PAGE 769
-
#define HV_KMRN_MODE_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 16)
#define HV_KMRN_MDIO_SLOW 0x0400
+#define BM_PORT_GEN_CFG BME1000_REG(BM_PORT_CTRL_PAGE, 17)
+
+#define CV_SMB_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 23)
+#define CV_SMB_CTRL_FORCE_SMBUS __BIT(0)
+
+#define HV_PM_CTRL BME1000_REG(770, 17)
+#define HV_PM_CTRL_K1_ENA __BIT(14)
+
#define IGP3_KMRN_DIAG BME1000_REG(770, 19)
#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS (1 << 1)
@@ -102,6 +109,17 @@
#define HV_MUX_DATA_CTRL_FORCE_SPEED (1 << 2)
#define HV_MUX_DATA_CTRL_GEN_TO_MAC (1 << 10)
+#define I218_ULP_CONFIG1 BME1000_REG(779, 16)
+#define I218_ULP_CONFIG1_START __BIT(0)
+#define I218_ULP_CONFIG1_IND __BIT(2)
+#define I218_ULP_CONFIG1_STICKY_ULP __BIT(4)
+#define I218_ULP_CONFIG1_INBAND_EXIT __BIT(5)
+#define I218_ULP_CONFIG1_WOL_HOST __BIT(6)
+#define I218_ULP_CONFIG1_RESET_TO_SMBUS __BIT(8)
+#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC __BIT(10)
+#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST __BIT(11)
+#define I218_ULP_CONFIG1_DIS_SMB_PERST __BIT(12)
+
#define BM_WUC_PAGE 800
#define BM_WUC BME1000_REG(BM_WUC_PAGE, 1)
#define BM_WUC_ADDRESS_OPCODE 0x11
@@ -110,5 +128,6 @@
#define BM_WUC_ENABLE_REG 17
#define BM_WUC_ENABLE_BIT (1 << 2)
#define BM_WUC_HOST_WU_BIT (1 << 4)
+#define BM_WUC_ME_WU_BIT (1 << 5)
#endif /* _DEV_MII_INBMPHYREG_H_ */
diff -r db73c5fa7f07 -r ece0b5bace54 sys/dev/mii/mii.h
--- a/sys/dev/mii/mii.h Mon Dec 12 07:04:31 2016 +0000
+++ b/sys/dev/mii/mii.h Mon Dec 12 07:18:29 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mii.h,v 1.18 2014/06/16 14:43:22 msaitoh Exp $ */
+/* $NetBSD: mii.h,v 1.18.2.1 2016/12/12 07:18:29 snj Exp $ */
/*
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
@@ -35,6 +35,8 @@
*/
#define MII_NPHY 32 /* max # of PHYs per MII */
+#define MII_ADDRBITS 5 /* Register address bits (0x00..0x1f) */
+#define MII_ADDRMASK 0x1f /* Address mask */
/*
* MII commands, used if a device must drive the MII lines
@@ -198,9 +200,9 @@
#define PSECR_PSEDIS 0x0000 /* PSE Disabled */
#define MII_PSESR 0x0c /* PSE status register */
-#define PSESR_PWRDENIED 0x1000 /* Power Deined */
+#define PSESR_PWRDENIED 0x1000 /* Power Denied */
#define PSESR_VALSIG 0x0800 /* Valid PD signature detected */
-#define PSESR_INVALSIG 0x0400 /* Inalid PD signature detected */
+#define PSESR_INVALSIG 0x0400 /* Invalid PD signature detected */
#define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */
#define PSESR_OVERLOAD 0x0100 /* Overload condition detected */
#define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */
diff -r db73c5fa7f07 -r ece0b5bace54 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Mon Dec 12 07:04:31 2016 +0000
+++ b/sys/dev/pci/if_wm.c Mon Dec 12 07:18:29 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.289.2.10 2016/12/09 05:27:30 snj Exp $ */
+/* $NetBSD: if_wm.c,v 1.289.2.11 2016/12/12 07:18:29 snj Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -84,7 +84,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.289.2.10 2016/12/09 05:27:30 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.289.2.11 2016/12/12 07:18:29 snj Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -135,14 +135,16 @@
#include <dev/pci/if_wmvar.h>
#ifdef WM_DEBUG
-#define WM_DEBUG_LINK 0x01
-#define WM_DEBUG_TX 0x02
-#define WM_DEBUG_RX 0x04
-#define WM_DEBUG_GMII 0x08
-#define WM_DEBUG_MANAGE 0x10
-#define WM_DEBUG_NVM 0x20
+#define WM_DEBUG_LINK __BIT(0)
+#define WM_DEBUG_TX __BIT(1)
+#define WM_DEBUG_RX __BIT(2)
+#define WM_DEBUG_GMII __BIT(3)
+#define WM_DEBUG_MANAGE __BIT(4)
+#define WM_DEBUG_NVM __BIT(5)
+#define WM_DEBUG_INIT __BIT(6)
+#define WM_DEBUG_LOCK __BIT(7)
int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
- | WM_DEBUG_MANAGE | WM_DEBUG_NVM;
+ | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT | WM_DEBUG_LOCK;
#define DPRINTF(x, y) if (wm_debug & (x)) printf y
#else
@@ -256,6 +258,14 @@
36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
};
+struct wm_softc;
+
+struct wm_phyop {
+ int (*acquire)(struct wm_softc *);
+ void (*release)(struct wm_softc *);
+ int reset_delay_us;
+};
+
/*
* Software state per device.
*/
@@ -270,6 +280,10 @@
bus_space_tag_t sc_flasht; /* flash registers space tag */
bus_space_handle_t sc_flashh; /* flash registers space handle */
bus_size_t sc_flashs; /* flash registers space size */
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