[src/trunk]: src/sys/arch/x86/x86 On i386 (but not on amd64) we can enable SS...

[tls <tls%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/4943effb075f
branches:  trunk
changeset: 821757:4943effb075f
user:      tls <tls%NetBSD.org@localhost>
date:      Thu Feb 16 15:00:30 2017 +0000

description:
On i386 (but not on amd64) we can enable SSE comparatively very late, when
probing/attaching the FPU.  This is a problem for cpu_rng with the VIA
processors because, by design, cpu_rng attaches, and the entropy subsystem
starts up, very early.

If SSE is not enabled, calls to any "PadLock" instructions (ACE, RNG)
on the VIA processors will trap, per the manual:
        linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261

All VIA CPUs with PadLock, or which match the model/stepping test as
possibly having PadLock, have SSE.  Just unconditionally enable it before
trying to turn the crypto block on.

Fixes crash at RNG attach time reported by Andrus V.; fix proposed by
jak@.

diffstat:

 sys/arch/x86/x86/identcpu.c |  18 +++++++++++++++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diffs (39 lines):

diff -r 73bd70cb6a56 -r 4943effb075f sys/arch/x86/x86/identcpu.c
--- a/sys/arch/x86/x86/identcpu.c       Thu Feb 16 14:00:26 2017 +0000
+++ b/sys/arch/x86/x86/identcpu.c       Thu Feb 16 15:00:30 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: identcpu.c,v 1.52 2017/02/02 08:57:04 maxv Exp $       */
+/*     $NetBSD: identcpu.c,v 1.53 2017/02/16 15:00:30 tls Exp $        */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.52 2017/02/02 08:57:04 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.53 2017/02/16 15:00:30 tls Exp $");
 
 #include "opt_xen.h"
 
@@ -551,7 +551,19 @@
                        }
                    }
 
-                   /* Actually do the enables. */
+                   /*
+                    * Actually do the enables.  It's a little gross,
+                    * but per the PadLock programming guide, "Enabling
+                    * PadLock", condition 3, we must enable SSE too or
+                    * else the first use of RNG or ACE instructions
+                    * will generate a trap.
+                    *
+                    * We must do this early because of kernel RNG
+                    * initialization but it is safe without the full
+                    * FPU-detect as all these CPUs have SSE.
+                    */
+                   lcr4(rcr4() | CR4_OSFXSR);
+
                    if (rng_enable) {
                        msr = rdmsr(MSR_VIA_RNG);
                        msr |= MSR_VIA_RNG_ENABLE;