[src/trunk]: src/sys/arch/arm/arm Allow for 8KB page size. Add ARM_MMU_EXTEN...

To: source-changes-hg%NetBSD.org@localhost
Subject: [src/trunk]: src/sys/arch/arm/arm Allow for 8KB page size. Add ARM_MMU_EXTEN...
From: matt <matt%NetBSD.org@localhost>
Date: Tue, 07 Apr 2020 02:17:31 +0000
details:   https://anonhg.NetBSD.org/src/rev/48af4e702969
branches:  trunk
changeset: 795010:48af4e702969
user:      matt <matt%NetBSD.org@localhost>
date:      Sun Mar 30 01:15:03 2014 +0000

description:
Allow for 8KB page size.  Add ARM_MMU_EXTENDED support.
Add missing END()

diffstat:

 sys/arch/arm/arm/cpufunc_asm_arm10.S    |  17 ++++++++++++++-
 sys/arch/arm/arm/cpufunc_asm_arm11.S    |  32 ++++++++++++++++++++++++++----
 sys/arch/arm/arm/cpufunc_asm_arm11x6.S  |  24 +++++++---------------
 sys/arch/arm/arm/cpufunc_asm_arm3.S     |   3 +-
 sys/arch/arm/arm/cpufunc_asm_arm67.S    |   3 +-
 sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S |  28 +++++++++++++++++---------
 sys/arch/arm/arm/cpufunc_asm_arm8.S     |  18 ++++++++++++++++-
 sys/arch/arm/arm/cpufunc_asm_arm9.S     |  25 +++++++++++++++++++----
 sys/arch/arm/arm/cpufunc_asm_armv4.S    |   9 ++++++-
 sys/arch/arm/arm/cpufunc_asm_armv5.S    |   5 +--
 sys/arch/arm/arm/cpufunc_asm_armv5_ec.S |   5 +--
 sys/arch/arm/arm/cpufunc_asm_fa526.S    |  27 ++++++++++++++++++++++++-
 sys/arch/arm/arm/cpufunc_asm_ixp12x0.S  |   4 ++-
 sys/arch/arm/arm/cpufunc_asm_pj4b.S     |  34 ++++++++++++++++++++++----------
 sys/arch/arm/arm/cpufunc_asm_sa1.S      |  24 ++++++++++++++++++++++-
 sys/arch/arm/arm/cpufunc_asm_sa11x0.S   |   3 +-
 sys/arch/arm/arm/cpufunc_asm_sheeva.S   |   3 +-
 sys/arch/arm/arm/cpufunc_asm_xscale.S   |   8 ++++++-
 18 files changed, 204 insertions(+), 68 deletions(-)

diffs (truncated from 1014 to 300 lines):

diff -r f2ace59cc110 -r 48af4e702969 sys/arch/arm/arm/cpufunc_asm_arm10.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm10.S      Sun Mar 30 01:12:18 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm10.S      Sun Mar 30 01:15:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm10.S,v 1.10 2013/08/18 06:28:18 matt Exp $      */
+/*     $NetBSD: cpufunc_asm_arm10.S,v 1.11 2014/03/30 01:15:03 matt Exp $      */
 
 /*
  * Copyright (c) 2002 ARM Limited
@@ -33,6 +33,7 @@
  
 #include <machine/asm.h>
 #include <arm/locore.h>
+#include "assym.h"
 
 /*
  * TLB functions
@@ -40,12 +41,23 @@
 ENTRY(arm10_tlb_flushID_SE)
        mcr     p15, 0, r0, c8, c6, 1   /* flush D tlb single entry */
        mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
+#if PAGE_SIZE == 2 * L2_S_SIZE
+       add     r0, r0, #L2_S_SIZE
+       mcr     p15, 0, r0, c8, c6, 1   /* flush D tlb single entry */
+       mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
+#endif
        RET
+END(arm10_tlb_flushID_SE)
 
 ENTRY(arm10_tlb_flushI_SE)
        mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
+#if PAGE_SIZE == 2 * L2_S_SIZE
+       add     r0, r0, #L2_S_SIZE
+       mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
+#endif
        RET
-       
+END(arm10_tlb_flushI_SE)
+
 
 /*
  * Context switch.
@@ -67,3 +79,4 @@
        nop
        nop
        RET
+END(arm10_context_switch)
diff -r f2ace59cc110 -r 48af4e702969 sys/arch/arm/arm/cpufunc_asm_arm11.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm11.S      Sun Mar 30 01:12:18 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm11.S      Sun Mar 30 01:15:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm11.S,v 1.11 2014/02/20 17:27:46 matt Exp $      */
+/*     $NetBSD: cpufunc_asm_arm11.S,v 1.12 2014/03/30 01:15:03 matt Exp $      */
 
 /*
  * Copyright (c) 2002, 2005 ARM Limited
@@ -49,15 +49,17 @@
 #error arm11 does not have a VIVT cache.
 #endif
 
-       mcr     p15, 0, r0, c2, c0, 0   /* load new TTB */
-
        cmp     r1, #0
+       mcr     p15, 0, r0, c2, c0, 0   /* TTBR0 set */
+#ifdef ARM_MMU_EXTENDED
+       mcreq   p15, 0, r0, c2, c0, 1   /* TTBR1 set */
+#else
        mcrne   p15, 0, r0, c8, c7, 0   /* invalidate I+D TLBs */
        mcrne   p15, 0, r0, c7, c10, 4  /* drain write buffer */
+#endif
        RET
 END(arm11_setttb)
 
-
 /*
  * Context switch.
  *
@@ -69,9 +71,16 @@
         * We can assume that the caches will only contain kernel addresses
         * at this point.  So no need to flush them again.
         */
+#ifdef ARM_MMU_EXTENDED
+       cmp     r1, #0
+#endif
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       mcr     p15, 0, r0, c2, c0, 0   /* set the new TTB */
+       mcr     p15, 0, r0, c2, c0, 0   /* TTBR0 set */
+#ifdef ARM_MMU_EXTENDED
+       mcreq   p15, 0, r0, c2, c0, 1   /* TTBR1 set is asid 0 */
+#else
        mcr     p15, 0, r0, c8, c7, 0   /* and flush the I+D tlbs */
+#endif
 
        /* Paranoia -- make sure the pipeline is empty. */
        nop
@@ -96,6 +105,11 @@
        orr     r0, r0, r1              /* insert ASID into MVA */
 #endif
        mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
+#if PAGE_SIZE == 2 * L2_S_SIZE
+       add     r0, r0, #L2_S_SIZE
+       mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
+#endif
+
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        RET
@@ -113,6 +127,10 @@
        orr     r0, r0, r1              /* insert ASID into MVA */
 #endif
        mcr     p15, 0, r0, c8, c6, 1   /* flush D tlb single entry */
+#if PAGE_SIZE == 2 * L2_S_SIZE
+       add     r0, r0, #L2_S_SIZE
+       mcr     p15, 0, r0, c8, c6, 1   /* flush D tlb single entry */
+#endif
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        RET
@@ -130,6 +148,10 @@
        orr     r0, r0, r1              /* insert ASID into MVA */
 #endif
        mcr     p15, 0, r0, c8, c7, 1   /* flush I+D tlb single entry */
+#if PAGE_SIZE == 2 * L2_S_SIZE
+       add     r0, r0, #L2_S_SIZE
+       mcr     p15, 0, r0, c8, c7, 1   /* flush I+D tlb single entry */
+#endif
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        RET
diff -r f2ace59cc110 -r 48af4e702969 sys/arch/arm/arm/cpufunc_asm_arm11x6.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm11x6.S    Sun Mar 30 01:12:18 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm11x6.S    Sun Mar 30 01:15:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm11x6.S,v 1.3 2013/08/18 06:28:18 matt Exp $     */
+/*     $NetBSD: cpufunc_asm_arm11x6.S,v 1.4 2014/03/30 01:15:03 matt Exp $     */
 
 /*
  * Copyright (c) 2007 Microsoft
@@ -63,7 +63,7 @@
 #include <machine/asm.h>
 #include <arm/locore.h>
 
-RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.3 2013/08/18 06:28:18 matt Exp $")
+RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.4 2014/03/30 01:15:03 matt Exp $")
 
 #if 0
 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -114,37 +114,27 @@
        mcr     p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
 #endif
 
-ENTRY(arm11x6_setttb)
-#ifdef PMAP_CACHE_VIVT
-       Flush_D_cache(r2)
-       Invalidate_I_cache(r2, r3)
-#else
-       mov     r2, #0
-#endif
-       mcr     p15, 0, r0, c2, c0, 0   /* load new TTB */
-
-       cmp     r1, #0
-       mcrne   p15, 0, r2, c8, c7, 0   /* invalidate I+D TLBs */
-       mcrne   p15, 0, r2, c7, c10, 4  /* drain write buffer */
-       RET
-
 ENTRY_NP(arm11x6_idcache_wbinv_all)
        Flush_D_cache(r0)
        Invalidate_I_cache(r0, r1)
        RET
+END(arm11x6_idcache_wbinv_all)
 
 ENTRY_NP(arm11x6_dcache_wbinv_all)
        Flush_D_cache(r0)
        RET
+END(arm11x6_dcache_wbinv_all)
 
 ENTRY_NP(arm11x6_icache_sync_all)
        Flush_D_cache(r0)
        Invalidate_I_cache(r0, r1)
        RET
+END(arm11x6_icache_sync_all)
 
 ENTRY_NP(arm11x6_flush_prefetchbuf)
        mcr     p15, 0, r0, c7, c5, 4   /* Flush Prefetch Buffer */
        RET
+END(arm11x6_flush_prefetchbuf)
 
 ENTRY_NP(arm11x6_icache_sync_range)
        add     r1, r1, r0
@@ -171,6 +161,7 @@
        mcrr    p15, 0, r1, r0, c12     /* clean and invalidate D cache range */ /* XXXNH */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
        RET
+END(arm11x6_icache_sync_range)
 
 ENTRY_NP(arm11x6_idcache_wbinv_range)
        add     r1, r1, r0
@@ -197,6 +188,7 @@
        mcrr    p15, 0, r1, r0, c14     /* clean and invalidate D cache range */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
        RET
+END(arm11x6_idcache_wbinv_range)
 
 /*
  * Preload the cache before issuing the WFI by conditionally disabling the
diff -r f2ace59cc110 -r 48af4e702969 sys/arch/arm/arm/cpufunc_asm_arm3.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm3.S       Sun Mar 30 01:12:18 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm3.S       Sun Mar 30 01:15:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm3.S,v 1.3 2013/08/18 06:28:18 matt Exp $        */
+/*     $NetBSD: cpufunc_asm_arm3.S,v 1.4 2014/03/30 01:15:03 matt Exp $        */
 
 /*
  * Copyright (c) 1997,1998 Mark Brinicombe.
@@ -35,6 +35,7 @@
  * ARM3 assembly functions for CPU / MMU / TLB specific operations
  */
  
+#include "assym.h"
 #include <machine/asm.h>
 #include <arm/locore.h>
 
diff -r f2ace59cc110 -r 48af4e702969 sys/arch/arm/arm/cpufunc_asm_arm67.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm67.S      Sun Mar 30 01:12:18 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm67.S      Sun Mar 30 01:15:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm67.S,v 1.6 2013/08/18 06:28:18 matt Exp $       */
+/*     $NetBSD: cpufunc_asm_arm67.S,v 1.7 2014/03/30 01:15:03 matt Exp $       */
 
 /*
  * Copyright (c) 1997,1998 Mark Brinicombe.
@@ -35,6 +35,7 @@
  * ARM6/ARM7 assembly functions for CPU / MMU / TLB specific operations
  */
  
+#include "assym.h"
 #include <machine/asm.h>
 #include <arm/locore.h>
 
diff -r f2ace59cc110 -r 48af4e702969 sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S   Sun Mar 30 01:12:18 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S   Sun Mar 30 01:15:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.6 2013/08/18 06:28:18 matt Exp $    */
+/*     $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.7 2014/03/30 01:15:03 matt Exp $    */
 
 /*
  * Copyright (c) 2001 John Fremlin
@@ -34,6 +34,7 @@
  * ARM7TDMI assembly functions for CPU / MMU / TLB specific operations
  */
  
+#include "assym.h"
 #include <machine/asm.h>
 #include <arm/locore.h>
 
@@ -43,6 +44,13 @@
  * We need to clean and flush the cache as it uses virtual
  * addresses that are about to change.
  */
+
+/*
+ * Context switch.
+ *
+ * These are the CPU-specific parts of the context switcher cpu_switch()
+ * These functions actually perform the TTB reload.
+ */
 ENTRY(arm7tdmi_setttb)
        mov     r3, lr          /* ditto with lr */
        mov     r2, r1          /* store the flush flag in a safe place */
@@ -64,6 +72,8 @@
        bl      _C_LABEL(arm7tdmi_cache_flushID)
 
        mov     pc, r3
+END(arm7tdmi_setttb)
+STRONG_ALIAS(arm7tdmi_context_switch, arm7tdmi_setttb)
 
 /*
  * TLB functions
@@ -72,10 +82,16 @@
        mov     r0, #0
        mcr     p15, 0, r0, c8, c7, 0
        mov     pc, lr
+END(arm7tdmi_tlb_flushID)
 
 ENTRY(arm7tdmi_tlb_flushID_SE)
        mcr     p15, 0, r0, c8, c7, 1
+#if PAGE_SIZE == 2 * L2_S_SIZE
+       add     r0, r0, #L2_S_SIZE
+       mcr     p15, 0, r0, c8, c7, 1
+#endif
        mov     pc, lr
+END(arm7tdmi_tlb_flushID_SE)
 
 /*
  * Cache functions
@@ -90,12 +106,4 @@
        mov     r0, r0
 
        mov     pc, lr
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