[src/trunk]: src/sys/arch/arm/nvidia Add register definitions that will be ne...

[jakllsch <jakllsch%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f01c3f598525
branches:  trunk
changeset: 818104:f01c3f598525
user:      jakllsch <jakllsch%NetBSD.org@localhost>
date:      Mon Sep 26 20:08:58 2016 +0000

description:
Add register definitions that will be necessary for future
tegraxusbpadctl(4) changes.

diffstat:

 sys/arch/arm/nvidia/tegra_xusbpadreg.h |  27 ++++++++++++++++++++++++++-
 1 files changed, 26 insertions(+), 1 deletions(-)

diffs (41 lines):

diff -r 7824603a7188 -r f01c3f598525 sys/arch/arm/nvidia/tegra_xusbpadreg.h
--- a/sys/arch/arm/nvidia/tegra_xusbpadreg.h    Mon Sep 26 20:05:03 2016 +0000
+++ b/sys/arch/arm/nvidia/tegra_xusbpadreg.h    Mon Sep 26 20:08:58 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_xusbpadreg.h,v 1.1 2015/05/15 11:49:10 jmcneill Exp $ */
+/* $NetBSD: tegra_xusbpadreg.h,v 1.2 2016/09/26 20:08:58 jakllsch Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -118,6 +118,31 @@
 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5_REG         0x158
 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6_REG         0x15c
 
+#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN          __BIT(18)
+#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY      __BIT(17)
+#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN            __BIT(16)
+
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI                    __BIT(21)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2                      __BIT(20)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD                       __BIT(19)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW                 __BITS(15,14)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(pad)                ((pad >= 1) ? 0x0 : 0x3)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW                  __BITS(11,6)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL              0x0e
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL            __BITS(5,0)
+
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP              __BITS(10,9)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ           __BITS(6,3)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR                    __BIT(2)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP    __BIT(1)
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP    __BIT(0)
+
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK                  __BIT(13)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD                      __BIT(12)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL         __BITS(4,2)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL     0x5
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL                __BITS(1,0)
+
 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0                __BITS(27,26)
 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_PCIE   0
 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_USB3_SS        1