Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/external/bsd/dwc2/dist Resolve conflicts
details: https://anonhg.NetBSD.org/src/rev/23c9fb5d4ea1
branches: trunk
changeset: 790195:23c9fb5d4ea1
user: skrll <skrll%NetBSD.org@localhost>
date: Wed Sep 25 06:19:22 2013 +0000
description:
Resolve conflicts
diffstat:
sys/external/bsd/dwc2/dist/dwc2_core.c | 416 ++++++++++++++++++----------
sys/external/bsd/dwc2/dist/dwc2_core.h | 190 +++++++++---
sys/external/bsd/dwc2/dist/dwc2_coreintr.c | 8 +-
sys/external/bsd/dwc2/dist/dwc2_hcd.c | 172 ++--------
sys/external/bsd/dwc2/dist/dwc2_hcd.h | 23 +-
sys/external/bsd/dwc2/dist/dwc2_hcdddma.c | 12 +-
sys/external/bsd/dwc2/dist/dwc2_hcdintr.c | 71 +---
sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c | 44 +-
sys/external/bsd/dwc2/dist/dwc2_hw.h | 2 +-
9 files changed, 517 insertions(+), 421 deletions(-)
diffs (truncated from 1913 to 300 lines):
diff -r 5d9e441df1fd -r 23c9fb5d4ea1 sys/external/bsd/dwc2/dist/dwc2_core.c
--- a/sys/external/bsd/dwc2/dist/dwc2_core.c Wed Sep 25 05:41:15 2013 +0000
+++ b/sys/external/bsd/dwc2/dist/dwc2_core.c Wed Sep 25 06:19:22 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc2_core.c,v 1.2 2013/09/05 20:25:27 skrll Exp $ */
+/* $NetBSD: dwc2_core.c,v 1.3 2013/09/25 06:19:22 skrll Exp $ */
/*
* core.c - DesignWare HS OTG Controller common routines
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.2 2013/09/05 20:25:27 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.3 2013/09/25 06:19:22 skrll Exp $");
#include <sys/types.h>
#include <sys/bus.h>
@@ -101,12 +101,10 @@
*/
static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
{
- u32 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
- u32 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
u32 hcfg, val;
- if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
- fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
+ if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
+ hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
hsotg->core_params->ulpi_fs_ls > 0) ||
hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
/* Full speed PHY */
@@ -119,7 +117,7 @@
dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
hcfg = DWC2_READ_4(hsotg, HCFG);
hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
- hcfg |= val;
+ hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
DWC2_WRITE_4(hsotg, HCFG, hcfg);
}
@@ -256,7 +254,7 @@
static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
{
- u32 usbcfg, hs_phy_type, fs_phy_type;
+ u32 usbcfg;
if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
@@ -267,11 +265,8 @@
dwc2_hs_phy_init(hsotg, select_phy);
}
- hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
- fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
-
- if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
- fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
+ if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
+ hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
hsotg->core_params->ulpi_fs_ls > 0) {
dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
@@ -290,7 +285,7 @@
{
u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG);
- switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {
+ switch (hsotg->hw_params.arch) {
case GHWCFG2_EXT_DMA_ARCH:
dev_err(hsotg->dev, "External DMA Mode not supported\n");
return -EINVAL;
@@ -339,7 +334,7 @@
usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
- switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {
+ switch (hsotg->hw_params.op_mode) {
case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
if (hsotg->core_params->otg_cap ==
DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
@@ -400,21 +395,6 @@
/* Reset the Controller */
dwc2_core_reset(hsotg);
- dev_dbg(hsotg->dev, "num_dev_perio_in_ep=%d\n",
- hsotg->hwcfg4 >> GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT &
- GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK >>
- GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT);
-
- hsotg->total_fifo_size = hsotg->hwcfg3 >> GHWCFG3_DFIFO_DEPTH_SHIFT &
- GHWCFG3_DFIFO_DEPTH_MASK >> GHWCFG3_DFIFO_DEPTH_SHIFT;
- hsotg->rx_fifo_size = DWC2_READ_4(hsotg, GRXFSIZ);
- hsotg->nperio_tx_fifo_size =
- DWC2_READ_4(hsotg, GNPTXFSIZ) >> 16 & 0xffff;
-
- dev_dbg(hsotg->dev, "Total FIFO SZ=%d\n", hsotg->total_fifo_size);
- dev_dbg(hsotg->dev, "RxFIFO SZ=%d\n", hsotg->rx_fifo_size);
- dev_dbg(hsotg->dev, "NP TxFIFO SZ=%d\n", hsotg->nperio_tx_fifo_size);
-
/*
* This needs to happen in FS mode before any other programming occurs
*/
@@ -502,22 +482,18 @@
static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *params = hsotg->core_params;
- u32 rxfsiz, nptxfsiz, ptxfsiz, hptxfsiz, dfifocfg;
+ u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
if (!params->enable_dynamic_fifo)
return;
- dev_dbg(hsotg->dev, "Total FIFO Size=%d\n", hsotg->total_fifo_size);
- dev_dbg(hsotg->dev, "Rx FIFO Size=%d\n", params->host_rx_fifo_size);
- dev_dbg(hsotg->dev, "NP Tx FIFO Size=%d\n",
- params->host_nperio_tx_fifo_size);
- dev_dbg(hsotg->dev, "P Tx FIFO Size=%d\n",
- params->host_perio_tx_fifo_size);
-
/* Rx FIFO */
- dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n",
- DWC2_READ_4(hsotg, GRXFSIZ));
- DWC2_WRITE_4(hsotg, GRXFSIZ, params->host_rx_fifo_size);
+ grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ);
+ dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
+ grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
+ grxfsiz |= params->host_rx_fifo_size <<
+ GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
+ DWC2_WRITE_4(hsotg, GRXFSIZ, grxfsiz);
dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", DWC2_READ_4(hsotg, GRXFSIZ));
/* Non-periodic Tx FIFO */
@@ -534,29 +510,28 @@
/* Periodic Tx FIFO */
dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
DWC2_READ_4(hsotg, HPTXFSIZ));
- ptxfsiz = params->host_perio_tx_fifo_size <<
- FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
- ptxfsiz |= (params->host_rx_fifo_size +
- params->host_nperio_tx_fifo_size) <<
- FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
- DWC2_WRITE_4(hsotg, HPTXFSIZ, ptxfsiz);
+ hptxfsiz = params->host_perio_tx_fifo_size <<
+ FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
+ hptxfsiz |= (params->host_rx_fifo_size +
+ params->host_nperio_tx_fifo_size) <<
+ FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
+ DWC2_WRITE_4(hsotg, HPTXFSIZ, hptxfsiz);
dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
DWC2_READ_4(hsotg, HPTXFSIZ));
if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
- hsotg->snpsid <= DWC2_CORE_REV_2_94a) {
+ hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
/*
* Global DFIFOCFG calculation for Host mode -
* include RxFIFO, NPTXFIFO and HPTXFIFO
*/
dfifocfg = DWC2_READ_4(hsotg, GDFIFOCFG);
- rxfsiz = DWC2_READ_4(hsotg, GRXFSIZ) & 0x0000ffff;
- nptxfsiz = DWC2_READ_4(hsotg, GNPTXFSIZ) >> 16 & 0xffff;
- hptxfsiz = DWC2_READ_4(hsotg, HPTXFSIZ) >> 16 & 0xffff;
dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
- dfifocfg |= (rxfsiz + nptxfsiz + hptxfsiz) <<
- GDFIFOCFG_EPINFOBASE_SHIFT &
- GDFIFOCFG_EPINFOBASE_MASK;
+ dfifocfg |= (params->host_rx_fifo_size +
+ params->host_nperio_tx_fifo_size +
+ params->host_perio_tx_fifo_size) <<
+ GDFIFOCFG_EPINFOBASE_SHIFT &
+ GDFIFOCFG_EPINFOBASE_MASK;
DWC2_WRITE_4(hsotg, GDFIFOCFG, dfifocfg);
}
}
@@ -590,7 +565,7 @@
/*
* This bit allows dynamic reloading of the HFIR register during
- * runtime. This bit needs to be programmed during inital configuration
+ * runtime. This bit needs to be programmed during initial configuration
* and its value must not be changed during runtime.
*/
if (hsotg->core_params->reload_ctl > 0) {
@@ -600,10 +575,9 @@
}
if (hsotg->core_params->dma_desc_enable > 0) {
- u32 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
-
- if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||
- !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
+ u32 op_mode = hsotg->hw_params.op_mode;
+ if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
+ !hsotg->hw_params.dma_desc_enable ||
op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
@@ -881,26 +855,20 @@
dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
hc_num, hcchar);
- dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, hc_num);
+ dev_vdbg(hsotg->dev, "%s: Channel %d\n",
+ __func__, hc_num);
dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
- hcchar >> HCCHAR_DEVADDR_SHIFT &
- HCCHAR_DEVADDR_MASK >> HCCHAR_DEVADDR_SHIFT);
+ chan->dev_addr);
dev_vdbg(hsotg->dev, " Ep Num: %d\n",
- hcchar >> HCCHAR_EPNUM_SHIFT &
- HCCHAR_EPNUM_MASK >> HCCHAR_EPNUM_SHIFT);
+ chan->ep_num);
dev_vdbg(hsotg->dev, " Is In: %d\n",
- !!(hcchar & HCCHAR_EPDIR));
+ chan->ep_is_in);
dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
- !!(hcchar & HCCHAR_LSPDDEV));
+ chan->speed == USB_SPEED_LOW);
dev_vdbg(hsotg->dev, " Ep Type: %d\n",
- hcchar >> HCCHAR_EPTYPE_SHIFT &
- HCCHAR_EPTYPE_MASK >> HCCHAR_EPTYPE_SHIFT);
+ chan->ep_type);
dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
- hcchar >> HCCHAR_MPS_SHIFT &
- HCCHAR_MPS_MASK >> HCCHAR_MPS_SHIFT);
- dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
- hcchar >> HCCHAR_MULTICNT_SHIFT &
- HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
+ chan->max_packet);
}
/* Program the HCSPLT register for SPLITs */
@@ -930,8 +898,7 @@
dev_vdbg(hsotg->dev, " is_in %d\n",
chan->ep_is_in);
dev_vdbg(hsotg->dev, " Max Pkt %d\n",
- hcchar >> HCCHAR_MPS_SHIFT &
- HCCHAR_MPS_MASK >> HCCHAR_MPS_SHIFT);
+ chan->max_packet);
dev_vdbg(hsotg->dev, " xferlen %d\n",
chan->xfer_len);
}
@@ -1380,14 +1347,14 @@
dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
chan->hc_num);
dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
- hctsiz >> TSIZ_XFERSIZE_SHIFT &
- TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
+ (hctsiz & TSIZ_XFERSIZE_MASK) >>
+ TSIZ_XFERSIZE_SHIFT);
dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
- hctsiz >> TSIZ_PKTCNT_SHIFT &
- TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
+ (hctsiz & TSIZ_PKTCNT_MASK) >>
+ TSIZ_PKTCNT_SHIFT);
dev_vdbg(hsotg->dev, " Start PID: %d\n",
- hctsiz >> TSIZ_SC_MC_PID_SHIFT &
- TSIZ_SC_MC_PID_MASK >> TSIZ_SC_MC_PID_SHIFT);
+ (hctsiz & TSIZ_SC_MC_PID_MASK) >>
+ TSIZ_SC_MC_PID_SHIFT);
}
if (hsotg->core_params->dma_enable > 0) {
@@ -1431,8 +1398,8 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
- hcchar >> HCCHAR_MULTICNT_SHIFT &
- HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
+ (hcchar & HCCHAR_MULTICNT_MASK) >>
+ HCCHAR_MULTICNT_SHIFT);
DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar);
if (dbg_hc(chan))
@@ -1520,8 +1487,8 @@
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
- hcchar >> HCCHAR_MULTICNT_SHIFT &
- HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
+ (hcchar & HCCHAR_MULTICNT_MASK) >>
+ HCCHAR_MULTICNT_SHIFT);
DWC2_WRITE_4(hsotg, HCCHAR(chan->hc_num), hcchar);
if (dbg_hc(chan))
@@ -1655,18 +1622,16 @@
u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
{
u32 usbcfg;
- u32 hwcfg2;
u32 hprt0;
int clock = 60; /* default value */
usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
- hwcfg2 = DWC2_READ_4(hsotg, GHWCFG2);
hprt0 = DWC2_READ_4(hsotg, HPRT0);
Home |
Main Index |
Thread Index |
Old Index