[src/netbsd-7]: src/sys/dev/pci Pull up following revision(s) (requested by m...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ba8cdf9083be
branches:  netbsd-7
changeset: 798693:ba8cdf9083be
user:      martin <martin%NetBSD.org@localhost>
date:      Fri Dec 12 18:56:16 2014 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #311):
        sys/dev/pci/ppb.c: revision 1.53
        sys/dev/pci/ppb.c: revision 1.54
        sys/dev/pci/pcireg.h: revision 1.96
- Modify message of PCIe capability version. This field (PCIE_XCAP_VER_MASK)
  is not specification's version number but the capability structure's version
  number. To avoid confusion, print "PCI Express capability version x".
- The max number of PCIe lane is not 16 but 32. Fix the bug using with macro.
- Use macro instead of magic number.
- Gb/s -> GT/s
Rename PCIE_XCAP_VER_* macros to avoid confusion.

diffstat:

 sys/dev/pci/pcireg.h |   6 +++---
 sys/dev/pci/ppb.c    |  40 +++++++++++++++++++++-------------------
 2 files changed, 24 insertions(+), 22 deletions(-)

diffs (105 lines):

diff -r 0e9f4cb2a444 -r ba8cdf9083be sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Fri Dec 12 16:44:35 2014 +0000
+++ b/sys/dev/pci/pcireg.h      Fri Dec 12 18:56:16 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.95 2014/06/09 11:08:05 msaitoh Exp $      */
+/*     $NetBSD: pcireg.h,v 1.95.2.1 2014/12/12 18:56:16 martin Exp $   */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -816,8 +816,8 @@
 #define        PCIE_XCAP_MASK          __BITS(31, 16)
 /* Capability Version */
 #define PCIE_XCAP_VER_MASK     __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK)
-#define         PCIE_XCAP_VER_1_0      __SHIFTIN(1, PCIE_XCAP_VER_MASK)
-#define         PCIE_XCAP_VER_2_0      __SHIFTIN(2, PCIE_XCAP_VER_MASK)
+#define         PCIE_XCAP_VER_1        __SHIFTIN(1, PCIE_XCAP_VER_MASK)
+#define         PCIE_XCAP_VER_2        __SHIFTIN(2, PCIE_XCAP_VER_MASK)
 #define        PCIE_XCAP_TYPE_MASK     __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK)
 #define         PCIE_XCAP_TYPE_PCIE_DEV __SHIFTIN(0x0, PCIE_XCAP_TYPE_MASK)
 #define         PCIE_XCAP_TYPE_PCI_DEV __SHIFTIN(0x1, PCIE_XCAP_TYPE_MASK)
diff -r 0e9f4cb2a444 -r ba8cdf9083be sys/dev/pci/ppb.c
--- a/sys/dev/pci/ppb.c Fri Dec 12 16:44:35 2014 +0000
+++ b/sys/dev/pci/ppb.c Fri Dec 12 18:56:16 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ppb.c,v 1.52 2013/04/21 19:59:41 msaitoh Exp $ */
+/*     $NetBSD: ppb.c,v 1.52.10.1 2014/12/12 18:56:16 martin Exp $     */
 
 /*
  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.52 2013/04/21 19:59:41 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.52.10.1 2014/12/12 18:56:16 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -108,17 +108,17 @@
                                &off, &reg))
                return; /* Not a PCIe device */
 
-       aprint_normal_dev(self, "PCI Express ");
+       aprint_normal_dev(self, "PCI Express capability version ");
        switch (reg & PCIE_XCAP_VER_MASK) {
-       case PCIE_XCAP_VER_1_0:
-               aprint_normal("1.0");
+       case PCIE_XCAP_VER_1:
+               aprint_normal("1");
                break;
-       case PCIE_XCAP_VER_2_0:
-               aprint_normal("2.0");
+       case PCIE_XCAP_VER_2:
+               aprint_normal("2");
                break;
        default:
                aprint_normal_dev(self,
-                   "version unsupported (0x%" PRIxMAX ")\n",
+                   "unsupported (0x%" PRIxMAX ")\n",
                    __SHIFTOUT(reg, PCIE_XCAP_VER_MASK));
                return;
        }
@@ -155,29 +155,31 @@
        case PCIE_XCAP_TYPE_ROOT:
        case PCIE_XCAP_TYPE_DOWN:
        case PCIE_XCAP_TYPE_PCI2PCIE:
-               reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x0c);
-               u_int mlw = (reg >> 4) & 0x1f;
-               u_int mls = (reg >> 0) & 0x0f;
+               reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP);
+               u_int mlw = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
+               u_int mls = __SHIFTOUT(reg, PCIE_LCAP_MAX_SPEED);
+
                if (mls < __arraycount(pcie_linkspeed_strings)) {
-                       aprint_normal("> x%d @ %sGb/s\n",
+                       aprint_normal("> x%d @ %sGT/s\n",
                            mlw, pcie_linkspeed_strings[mls]);
                } else {
-                       aprint_normal("> x%d @ %d.%dGb/s\n",
+                       aprint_normal("> x%d @ %d.%dGT/s\n",
                            mlw, (mls * 25) / 10, (mls * 25) % 10);
                }
 
-               reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x10);
-               if (reg & __BIT(29)) {  /* DLLA */
-                       u_int lw = (reg >> 20) & 0x1f;
-                       u_int ls = (reg >> 16) & 0x0f;
+               reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCSR);
+               if (reg & PCIE_LCSR_DLACTIVE) { /* DLLA */
+                       u_int lw = __SHIFTOUT(reg, PCIE_LCSR_NLW);
+                       u_int ls = __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED);
+
                        if (lw != mlw || ls != mls) {
                                if (ls < __arraycount(pcie_linkspeed_strings)) {
                                        aprint_normal_dev(self,
-                                           "link is x%d @ %sGb/s\n",
+                                           "link is x%d @ %sGT/s\n",
                                            lw, pcie_linkspeed_strings[ls]);
                                } else {
                                        aprint_normal_dev(self,
-                                           "link is x%d @ %d.%dGb/s\n",
+                                           "link is x%d @ %d.%dGT/s\n",
                                            lw, (ls * 25) / 10, (ls * 25) % 10);
                                }
                        }