[src/trunk]: src/sys/arch/sparc64 sun4v: extend dmmu_set_secondary_context() ...

[palle <palle%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/88938389cb1c
branches:  trunk
changeset: 813577:88938389cb1c
user:      palle <palle%NetBSD.org@localhost>
date:      Wed Feb 03 20:33:52 2016 +0000

description:
sun4v: extend dmmu_set_secondary_context() to handle both sun4u and sun4v. ok martin@

diffstat:

 sys/arch/sparc64/include/ctlreg.h |  14 ++------------
 sys/arch/sparc64/sparc64/locore.s |   4 ++--
 sys/arch/sparc64/sparc64/pmap.c   |  23 +++++++++++++++++++++--
 3 files changed, 25 insertions(+), 16 deletions(-)

diffs (97 lines):

diff -r 3cb6bb0b5641 -r 88938389cb1c sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Wed Feb 03 19:03:50 2016 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Wed Feb 03 20:33:52 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ctlreg.h,v 1.62 2015/04/01 18:38:30 palle Exp $ */
+/*     $NetBSD: ctlreg.h,v 1.63 2016/02/03 20:33:52 palle Exp $ */
 
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath
@@ -55,7 +55,7 @@
 #define        ASI_PHYS_CACHED_LITTLE          0x1c    /* [4u] MMU bypass to main memory, little endian */
 #define        ASI_PHYS_NON_CACHED_LITTLE      0x1d    /* [4u] MMU bypass to I/O location, little endian */
 
-#define ASI_MMU                                0x21    /* [4v] MMU context control - both IMMU and DMMU */
+#define ASI_MMU_CONTEXTID              0x21    /* [4v] MMU context control - both IMMU and DMMU */
 
 #define        ASI_NUCLEUS_QUAD_LDD            0x24    /* [4u] use w/LDDA to load 128-bit item */
 #define        ASI_QUEUE                       0x25    /* [4v] interrupt queue registers */
@@ -864,16 +864,6 @@
 SPARC64_ST_DEF64(stxa, uint64_t)
 
 
-/* set dmmu secondary context */
-static __inline void
-dmmu_set_secondary_context(uint ctx)
-{
-       __asm volatile(
-               "stxa %0,[%1]%2;        "
-               "membar #Sync           "
-               : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU)
-               : "memory");
-}
 
 /* flush address from data cache */
 #define        flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc)))
diff -r 3cb6bb0b5641 -r 88938389cb1c sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Wed Feb 03 19:03:50 2016 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Wed Feb 03 20:33:52 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.386 2015/11/06 15:30:59 martin Exp $      */
+/*     $NetBSD: locore.s,v 1.387 2016/02/03 20:33:52 palle Exp $       */
 
 /*
  * Copyright (c) 2006-2010 Matthew R. Green
@@ -129,7 +129,7 @@
        
 #ifdef SUN4V
        .macro  SET_MMU_CONTEXTID_SUN4V ctxid,ctx
-       stxa    \ctxid, [\ctx] ASI_MMU;
+       stxa    \ctxid, [\ctx] ASI_MMU_CONTEXTID;
        .endm
 #endif 
                
diff -r 3cb6bb0b5641 -r 88938389cb1c sys/arch/sparc64/sparc64/pmap.c
--- a/sys/arch/sparc64/sparc64/pmap.c   Wed Feb 03 19:03:50 2016 +0000
+++ b/sys/arch/sparc64/sparc64/pmap.c   Wed Feb 03 20:33:52 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.300 2015/11/27 13:51:24 joerg Exp $ */
+/*     $NetBSD: pmap.c,v 1.301 2016/02/03 20:33:52 palle Exp $ */
 /*
  *
  * Copyright (C) 1996-1999 Eduardo Horvath.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.300 2015/11/27 13:51:24 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.301 2016/02/03 20:33:52 palle Exp $");
 
 #undef NO_VCACHE /* Don't forget the locked TLB in dostart */
 #define        HWREF
@@ -158,6 +158,25 @@
 
 static void ctx_free(struct pmap *, struct cpu_info *);
 
+/* set dmmu secondary context */
+static __inline void
+dmmu_set_secondary_context(uint ctx)
+{
+       if (!CPU_ISSUN4V)
+               __asm volatile(
+                       "stxa %0,[%1]%2;        "
+                       "membar #Sync           "
+                       : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU)
+                       : "memory");
+       else
+               __asm volatile(
+                       "stxa %0,[%1]%2;        "
+                       "membar #Sync           "
+                       : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_MMU_CONTEXTID)
+                       : "memory");
+               
+}
+
 /*
  * Check if any MMU has a non-zero context
  */