[src/trunk]: src/sys/arch/x86/x86 Whitespace fix. No functional change.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/87a5dbadd4f6
branches:  trunk
changeset: 931019:87a5dbadd4f6
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Apr 20 04:17:51 2020 +0000

description:
Whitespace fix. No functional change.

diffstat:

 sys/arch/x86/x86/identcpu.c |  20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diffs (90 lines):

diff -r 8508924297f3 -r 87a5dbadd4f6 sys/arch/x86/x86/identcpu.c
--- a/sys/arch/x86/x86/identcpu.c       Mon Apr 20 03:57:02 2020 +0000
+++ b/sys/arch/x86/x86/identcpu.c       Mon Apr 20 04:17:51 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: identcpu.c,v 1.105 2020/04/09 02:07:01 christos Exp $  */
+/*     $NetBSD: identcpu.c,v 1.106 2020/04/20 04:17:51 msaitoh Exp $   */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.105 2020/04/09 02:07:01 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.106 2020/04/20 04:17:51 msaitoh Exp $");
 
 #include "opt_xen.h"
 
@@ -62,7 +62,7 @@
 
 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO;
 
-static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 
+static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] =
        AMD_L2L3CACHE_INFO;
 
 int cpu_vendor;
@@ -82,7 +82,7 @@
        CPUVENDOR_INTEL, CPUCLASS_386,  /* CPU_386SX */
        CPUVENDOR_INTEL, CPUCLASS_386,  /* CPU_386   */
        CPUVENDOR_INTEL, CPUCLASS_486,  /* CPU_486SX */
-       CPUVENDOR_INTEL, CPUCLASS_486,  /* CPU_486   */
+       CPUVENDOR_INTEL, CPUCLASS_486,  /* CPU_486   */
        CPUVENDOR_CYRIX, CPUCLASS_486,  /* CPU_486DLC */
        CPUVENDOR_CYRIX, CPUCLASS_486,  /* CPU_6x86 */
        CPUVENDOR_NEXGEN, CPUCLASS_386, /* CPU_NX586 */
@@ -174,7 +174,7 @@
        int iterations, i, j;
        uint8_t desc;
 
-       if (cpuid_level >= 2) { 
+       if (cpuid_level >= 2) {
                /* Parse the cache info from `cpuid leaf 2', if we have it. */
                x86_cpuid(2, descs);
                iterations = descs[0] & 0xff;
@@ -488,7 +488,7 @@
         */
        cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08);
 
-       /* 
+       /*
         * Do not disable the TSC on the Geode GX, it's reported to
         * work fine.
         */
@@ -525,7 +525,7 @@
 
        if (cpu_vendor != CPUVENDOR_IDT ||
            CPUID_TO_FAMILY(ci->ci_signature) != 5)
-               return;
+               return;
 
        /* WinChip C6 */
        if (CPUID_TO_MODEL(ci->ci_signature) == 4)
@@ -556,7 +556,7 @@
                 *
                 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet"
                 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf
-                * 
+                *
                 * 1. The CMPXCHG8B instruction is provided and always enabled,
                 *    however, it appears disabled in the corresponding CPUID
                 *    function bit 0 to avoid a bug in an early version of
@@ -646,7 +646,7 @@
        if (ci->ci_feat_val[4] & CPUID_VIA_DO_ACE) {
                msr = rdmsr(MSR_VIA_ACE);
                wrmsr(MSR_VIA_ACE, msr & ~VIA_ACE_ALTINST);
-       } 
+       }
 
        /*
         * Determine L1 cache/TLB info.
@@ -714,7 +714,7 @@
 
        if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 ||
            CPUID_TO_FAMILY(ci->ci_signature) != 5)
-               return;
+               return;
 
        cpu_probe_cyrix_cmn(ci);
        cpu_probe_amd_cache(ci);