[pkgsrc/trunk]: pkgsrc/emulators/qemu Two fixes

[skrll <skrll%pkgsrc.org@localhost>]

details:   https://anonhg.NetBSD.org/pkgsrc/rev/439382cb3709
branches:  trunk
changeset: 431202:439382cb3709
user:      skrll <skrll%pkgsrc.org@localhost>
date:      Sun May 10 11:33:23 2020 +0000

description:
Two fixes
- make qemu on aarch64 work (needs fixes in base OS)
- don't assert hppa lasi imr, but simply store the know interrupt bits

bump PKGREVISION

diffstat:

 emulators/qemu/Makefile                            |   4 +-
 emulators/qemu/distinfo                            |   5 +-
 emulators/qemu/patches/patch-accel_tcg_user-exec.c |  49 +++++++++++++++++++--
 emulators/qemu/patches/patch-hw_hppa_lasi.c        |  14 ++++++
 4 files changed, 62 insertions(+), 10 deletions(-)

diffs (135 lines):

diff -r f96e85738b35 -r 439382cb3709 emulators/qemu/Makefile
--- a/emulators/qemu/Makefile   Sun May 10 11:32:14 2020 +0000
+++ b/emulators/qemu/Makefile   Sun May 10 11:33:23 2020 +0000
@@ -1,7 +1,7 @@
-# $NetBSD: Makefile,v 1.239 2020/05/06 14:04:29 adam Exp $
+# $NetBSD: Makefile,v 1.240 2020/05/10 11:33:23 skrll Exp $
 
 DISTNAME=      qemu-5.0.0
-PKGREVISION=   1
+PKGREVISION=   2
 CATEGORIES=    emulators
 MASTER_SITES=  https://download.qemu.org/
 EXTRACT_SUFX=  .tar.xz
diff -r f96e85738b35 -r 439382cb3709 emulators/qemu/distinfo
--- a/emulators/qemu/distinfo   Sun May 10 11:32:14 2020 +0000
+++ b/emulators/qemu/distinfo   Sun May 10 11:33:23 2020 +0000
@@ -1,4 +1,4 @@
-$NetBSD: distinfo,v 1.158 2020/04/30 17:16:04 adam Exp $
+$NetBSD: distinfo,v 1.159 2020/05/10 11:33:23 skrll Exp $
 
 SHA1 (qemu-5.0.0.tar.xz) = 52d1c0e6025a212d4fde471e4d9b5913f2615f86
 RMD160 (qemu-5.0.0.tar.xz) = 58a704960cd712cf6c218216e8426a05948f6526
@@ -7,7 +7,7 @@
 SHA1 (patch-Makefile) = 85d24d842ad2f7e1e2ec6f0e0e3268c21ef9bf0d
 SHA1 (patch-accel_stubs_Makefile.objs) = 92266dc400ac1e97013f7f19ee4b7a63b42c7fc0
 SHA1 (patch-accel_stubs_nvmm-stub.c) = d66d47eabb8bb6728e777da7589b43d491adbcc8
-SHA1 (patch-accel_tcg_user-exec.c) = 86ee62f6e5c8cd7942cf0aa9c9f64e4b0879ff33
+SHA1 (patch-accel_tcg_user-exec.c) = ec5f3882c78763b4072daa41fd67e55da291c065
 SHA1 (patch-capstone_Makefile) = f59870031de8c4385a591362749ec82f57fd4c27
 SHA1 (patch-configure) = 993ed55b8e63c3022c5afc3dbc3f0eacbebdd61b
 SHA1 (patch-contrib_ivshmem-client_ivshmem-client.c) = 40c8751607cbf66a37e4c4e08f2664b864e2e984
@@ -15,6 +15,7 @@
 SHA1 (patch-cpus.c) = a319b7533daf3036c44411c4b26270b1fbb96009
 SHA1 (patch-hw_core_uboot__image.h) = 17eef02349343c5fcfb7a4069cb6f8fd11efcb59
 SHA1 (patch-hw_display_omap__dss.c) = 6b13242f28e32346bc70548c216c578d98fd3420
+SHA1 (patch-hw_hppa_lasi.c) = d7cb1e3988377e7962c962a85d1ccb58738501e4
 SHA1 (patch-hw_net_etraxfs__eth.c) = e5dd1661d60dbcd27b332403e0843500ba9544bc
 SHA1 (patch-hw_net_xilinx__axienet.c) = ebcd2676d64ce6f31e4a8c976d4fdf530ad5e8b7
 SHA1 (patch-hw_tpm_tpm__ioctl.h) = a350c1708e1f9d85e07c4c354068703a45174baf
diff -r f96e85738b35 -r 439382cb3709 emulators/qemu/patches/patch-accel_tcg_user-exec.c
--- a/emulators/qemu/patches/patch-accel_tcg_user-exec.c        Sun May 10 11:32:14 2020 +0000
+++ b/emulators/qemu/patches/patch-accel_tcg_user-exec.c        Sun May 10 11:33:23 2020 +0000
@@ -1,11 +1,11 @@
-$NetBSD: patch-accel_tcg_user-exec.c,v 1.1 2019/07/03 14:38:13 thorpej Exp $
+$NetBSD: patch-accel_tcg_user-exec.c,v 1.2 2020/05/10 11:33:23 skrll Exp $
 
 Fix building on NetBSD/arm by extracting the FSR value from the
 correct siginfo_t field.
 
---- accel/tcg/user-exec.c.orig 2019-07-03 13:09:53.530028621 +0000
-+++ accel/tcg/user-exec.c      2019-07-03 13:22:13.179596536 +0000
-@@ -448,6 +448,7 @@ int cpu_signal_handler(int host_signum, 
+--- accel/tcg/user-exec.c.orig 2020-04-28 16:49:24.000000000 +0000
++++ accel/tcg/user-exec.c
+@@ -492,6 +492,7 @@ int cpu_signal_handler(int host_signum, 
  
  #if defined(__NetBSD__)
  #include <ucontext.h>
@@ -13,7 +13,7 @@
  #endif
  
  int cpu_signal_handler(int host_signum, void *pinfo,
-@@ -456,6 +457,7 @@ int cpu_signal_handler(int host_signum, 
+@@ -500,6 +501,7 @@ int cpu_signal_handler(int host_signum, 
      siginfo_t *info = pinfo;
  #if defined(__NetBSD__)
      ucontext_t *uc = puc;
@@ -21,7 +21,7 @@
  #else
      ucontext_t *uc = puc;
  #endif
-@@ -470,10 +472,18 @@ int cpu_signal_handler(int host_signum, 
+@@ -514,15 +516,47 @@ int cpu_signal_handler(int host_signum, 
      pc = uc->uc_mcontext.arm_pc;
  #endif
  
@@ -40,3 +40,40 @@
      return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
  }
  
+ #elif defined(__aarch64__)
+ 
++#if defined(__NetBSD__)
++
++#include <ucontext.h>
++#include <sys/siginfo.h>
++
++int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
++{
++    ucontext_t *uc = puc;
++    siginfo_t *si = pinfo;
++    unsigned long pc;
++    int is_write;
++    uint32_t esr;
++
++    pc = uc->uc_mcontext.__gregs[_REG_PC];
++    esr = si->si_trap;
++
++    /* siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
++     * is 0b10010x: then bit 6 is the WnR bit
++     */
++    is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
++    return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask);
++}
++
++#else
+ #ifndef ESR_MAGIC
+ /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
+ #define ESR_MAGIC 0x45535201
+@@ -585,6 +619,7 @@ int cpu_signal_handler(int host_signum, 
+     }
+     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
+ }
++#endif
+ 
+ #elif defined(__s390__)
+ 
diff -r f96e85738b35 -r 439382cb3709 emulators/qemu/patches/patch-hw_hppa_lasi.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/emulators/qemu/patches/patch-hw_hppa_lasi.c       Sun May 10 11:33:23 2020 +0000
@@ -0,0 +1,14 @@
+$NetBSD: patch-hw_hppa_lasi.c,v 1.1 2020/05/10 11:33:23 skrll Exp $
+
+--- hw/hppa/lasi.c.orig        2020-04-28 16:49:24.000000000 +0000
++++ hw/hppa/lasi.c
+@@ -172,8 +172,7 @@ static MemTxResult lasi_chip_write_with_
+         /* read-only.  */
+         break;
+     case LASI_IMR:
+-        s->imr = val;  /* 0x20 ?? */
+-        assert((val & LASI_IRQ_BITS) == val);
++        s->imr = val & LASI_IRQ_BITS;
+         break;
+     case LASI_IPR:
+         /* Any write to IPR clears the register. */