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[src/trunk]: src/sys/arch Rockchip crypto engine RNG driver.
details: https://anonhg.NetBSD.org/src/rev/c1055b958ee8
branches: trunk
changeset: 932928:c1055b958ee8
user: riastradh <riastradh%NetBSD.org@localhost>
date: Sun May 17 19:57:25 2020 +0000
description:
Rockchip crypto engine RNG driver.
As found on the rk3288 and rk3399. This driver only supports the
TRNG, not the rest of the crypto engine, although it uses the AES unit
to do a self-test at attach time to verify that the engine works.
There seem to be two versions of the Rockchip crypto engine, v1 and
v2; this one is for v1. Can't name a driver `rkcryptov1' so we'll
clumsily call it `rkv1crypto' instead to leave room for `rkv2crypto'
later on.
The crypto binding derived from the Rockchip BSP Linux kernel, in the
location it appears on the rk3399, is in rk3399-crypto.dtsi, since
there doesn't seem to be a better place to put it at the moment among
this twisty maze of inclusions, all different.
diffstat:
sys/arch/arm/dts/rk3399-crypto.dtsi | 41 +++
sys/arch/arm/dts/rk3399-pinebook-pro.dts | 1 +
sys/arch/arm/dts/rk3399-rockpro64.dts | 4 +-
sys/arch/arm/rockchip/files.rockchip | 7 +-
sys/arch/arm/rockchip/rk3399_cru.c | 25 +-
sys/arch/arm/rockchip/rk_v1crypto.c | 385 +++++++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_v1crypto.h | 178 ++++++++++++++
sys/arch/evbarm/conf/GENERIC64 | 3 +-
8 files changed, 638 insertions(+), 6 deletions(-)
diffs (truncated from 737 to 300 lines):
diff -r 3dec110ee6b3 -r c1055b958ee8 sys/arch/arm/dts/rk3399-crypto.dtsi
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/dts/rk3399-crypto.dtsi Sun May 17 19:57:25 2020 +0000
@@ -0,0 +1,41 @@
+/* $NetBSD: rk3399-crypto.dtsi,v 1.1 2020/05/17 19:57:25 riastradh Exp $ */
+
+/*-
+ * Copyright (c) 2020 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/ {
+ crypto: crypto@ff8b8000 {
+ compatible = "rockchip,rk3288-crypto";
+ reg = <0x0 0xff8b8000 0x0 0x1000>;
+ clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>,
+ <&cru SCLK_CRYPTO1>, <&cru ACLK_DMAC1_PERILP>;
+ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
+ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
+ assigned-clock-rates = <150000000>, <100000000>;
+ resets = <&cru SRST_CRYPTO1>;
+ reset-names = "crypto-rst";
+ };
+};
diff -r 3dec110ee6b3 -r c1055b958ee8 sys/arch/arm/dts/rk3399-pinebook-pro.dts
--- a/sys/arch/arm/dts/rk3399-pinebook-pro.dts Sun May 17 19:43:31 2020 +0000
+++ b/sys/arch/arm/dts/rk3399-pinebook-pro.dts Sun May 17 19:57:25 2020 +0000
@@ -12,6 +12,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
+#include "rk3399-crypto.dtsi"
/ {
model = "Pine64 Pinebook Pro";
diff -r 3dec110ee6b3 -r c1055b958ee8 sys/arch/arm/dts/rk3399-rockpro64.dts
--- a/sys/arch/arm/dts/rk3399-rockpro64.dts Sun May 17 19:43:31 2020 +0000
+++ b/sys/arch/arm/dts/rk3399-rockpro64.dts Sun May 17 19:57:25 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399-rockpro64.dts,v 1.10 2019/12/19 00:52:29 jakllsch Exp $ */
+/* $NetBSD: rk3399-rockpro64.dts,v 1.11 2020/05/17 19:57:25 riastradh Exp $ */
/*-
* Copyright (c) 2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,6 +27,7 @@
*/
#include "../../../external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts"
+#include "rk3399-crypto.dtsi"
/ {
pwm-fan {
@@ -147,7 +148,6 @@
status = "okay";
};
#endif
-
};
&pinctrl {
diff -r 3dec110ee6b3 -r c1055b958ee8 sys/arch/arm/rockchip/files.rockchip
--- a/sys/arch/arm/rockchip/files.rockchip Sun May 17 19:43:31 2020 +0000
+++ b/sys/arch/arm/rockchip/files.rockchip Sun May 17 19:57:25 2020 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.23 2019/12/19 00:25:58 jakllsch Exp $
+# $NetBSD: files.rockchip,v 1.24 2020/05/17 19:57:25 riastradh Exp $
#
# Configuration info for Rockchip family SoCs
#
@@ -112,6 +112,11 @@
attach rki2s at fdt with rk_i2s
file arch/arm/rockchip/rk_i2s.c rk_i2s
+# Crypto engine v1
+device rkv1crypto
+attach rkv1crypto at fdt with rk_v1crypto
+file arch/arm/rockchip/rk_v1crypto.c rk_v1crypto
+
# SOC parameters
defflag opt_soc.h SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP
diff -r 3dec110ee6b3 -r c1055b958ee8 sys/arch/arm/rockchip/rk3399_cru.c
--- a/sys/arch/arm/rockchip/rk3399_cru.c Sun May 17 19:43:31 2020 +0000
+++ b/sys/arch/arm/rockchip/rk3399_cru.c Sun May 17 19:57:25 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399_cru.c,v 1.19 2020/01/04 13:32:32 jmcneill Exp $ */
+/* $NetBSD: rk3399_cru.c,v 1.20 2020/05/17 19:57:25 riastradh Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.19 2020/01/04 13:32:32 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.20 2020/05/17 19:57:25 riastradh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -847,6 +847,27 @@
0),
RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)),
+ /* Crypto */
+ RK_COMPOSITE(RK3399_SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_parents,
+ CLKSEL_CON(24), /* muxdiv_reg */
+ __BITS(7,6), /* mux_mask */
+ __BITS(4,0), /* div_mask */
+ CLKGATE_CON(7), /* gate_reg */
+ __BIT(7), /* gate_mask */
+ RK_COMPOSITE_ROUND_DOWN /*???*/),
+ RK_COMPOSITE(RK3399_SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_parents,
+ CLKSEL_CON(26), /* muxdiv_reg */
+ __BITS(7,6), /* mux_mask */
+ __BITS(4,0), /* div_mask */
+ CLKGATE_CON(8), /* gate_reg */
+ __BIT(7), /* gate_mask */
+ RK_COMPOSITE_ROUND_DOWN /*???*/),
+ RK_GATE(RK3399_HCLK_M_CRYPTO0, "hclk_m_crypto0", "pclk_perilp0", CLKGATE_CON(24), 5),
+ RK_GATE(RK3399_HCLK_S_CRYPTO0, "hclk_s_crypto0", "pclk_perilp0", CLKGATE_CON(24), 6),
+ RK_GATE(RK3399_HCLK_M_CRYPTO1, "hclk_m_crypto1", "pclk_perilp0", CLKGATE_CON(24), 14),
+ RK_GATE(RK3399_HCLK_S_CRYPTO1, "hclk_s_crypto1", "pclk_perilp0", CLKGATE_CON(24), 15),
+ RK_GATE(RK3399_ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "pclk_perilp", CLKGATE_CON(25), 6),
+
/* TSADC */
RK_COMPOSITE(RK3399_SCLK_TSADC, "clk_tsadc", mux_clk_tsadc_parents,
CLKSEL_CON(27), /* muxdiv_reg */
diff -r 3dec110ee6b3 -r c1055b958ee8 sys/arch/arm/rockchip/rk_v1crypto.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/rockchip/rk_v1crypto.c Sun May 17 19:57:25 2020 +0000
@@ -0,0 +1,385 @@
+/* $NetBSD: rk_v1crypto.c,v 1.1 2020/05/17 19:57:25 riastradh Exp $ */
+
+/*-
+ * Copyright (c) 2020 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Taylor R. Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * rk_v1crypto -- Rockchip crypto v1 driver
+ *
+ * This is just the RNG for now.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(1, "$NetBSD: rk_v1crypto.c,v 1.1 2020/05/17 19:57:25 riastradh Exp $");
+
+#include <sys/types.h>
+
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+#include <sys/mutex.h>
+#include <sys/rndsource.h>
+#include <sys/sysctl.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/rockchip/rk_v1crypto.h>
+
+struct rk_v1crypto_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ kmutex_t sc_lock;
+ struct krndsource sc_rndsource;
+ struct rk_v1crypto_sysctl {
+ struct sysctllog *cy_log;
+ const struct sysctlnode *cy_root_node;
+ } sc_sysctl;
+};
+
+static int rk_v1crypto_match(device_t, cfdata_t, void *);
+static void rk_v1crypto_attach(device_t, device_t, void *);
+static int rk_v1crypto_selftest(struct rk_v1crypto_softc *);
+static void rk_v1crypto_rndsource_attach(struct rk_v1crypto_softc *);
+static void rk_v1crypto_rng_get(size_t, void *);
+static void rk_v1crypto_sysctl_attach(struct rk_v1crypto_softc *);
+static int rk_v1crypto_sysctl_rng(SYSCTLFN_ARGS);
+static int rk_v1crypto_rng(struct rk_v1crypto_softc *,
+ uint32_t[static RK_V1CRYPTO_TRNG_NOUT]);
+
+static uint32_t
+RKC_READ(struct rk_v1crypto_softc *sc, bus_addr_t reg)
+{
+ return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);
+}
+
+static void
+RKC_WRITE(struct rk_v1crypto_softc *sc, bus_addr_t reg, uint32_t v)
+{
+ return bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, v);
+}
+
+static inline void
+RKC_CTRL(struct rk_v1crypto_softc *sc, uint16_t m, uint16_t v)
+{
+ uint32_t c = 0;
+
+ c |= __SHIFTIN(m, RK_V1CRYPTO_CTRL_MASK);
+ c |= __SHIFTIN(v, m);
+ RKC_WRITE(sc, RK_V1CRYPTO_CTRL, c);
+}
+
+CFATTACH_DECL_NEW(rk_v1crypto, sizeof(struct rk_v1crypto_softc),
+ rk_v1crypto_match, rk_v1crypto_attach, NULL, NULL);
+
+static const struct of_compat_data compat_data[] = {
+ {"rockchip,rk3288-crypto", 0},
+ {NULL}
+};
+
+static int
+rk_v1crypto_match(device_t parent, cfdata_t cf, void *aux)
+{
+ const struct fdt_attach_args *const faa = aux;
+
+ return of_match_compat_data(faa->faa_phandle, compat_data);
+}
+
+static void
+rk_v1crypto_attach(device_t parent, device_t self, void *aux)
+{
+ static const char *const clks[] = {"aclk", "hclk", "sclk", "apb_pclk"};
+ struct rk_v1crypto_softc *const sc = device_private(self);
+ const struct fdt_attach_args *const faa = aux;
+ bus_addr_t addr;
+ bus_size_t size;
+ const int phandle = faa->faa_phandle;
+ struct fdtbus_reset *rst;
+ unsigned i;
+ uint32_t ctrl;
+
+ fdtbus_clock_assign(phandle);
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
+
+ /* Get and map device registers. */
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ /* Enable the clocks. */
+ for (i = 0; i < __arraycount(clks); i++) {
+ if (fdtbus_clock_enable(phandle, clks[i], true) != 0) {
+ aprint_error(": couldn't enable %s clock\n", clks[i]);
+ return;
+ }
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