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[src/trunk]: src/sys/arch/mips Use the correct config3 field name (ULRI) for ...
details: https://anonhg.NetBSD.org/src/rev/c6153ba9549d
branches: trunk
changeset: 934485:c6153ba9549d
user: simonb <simonb%NetBSD.org@localhost>
date: Sat Jun 13 14:39:07 2020 +0000
description:
Use the correct config3 field name (ULRI) for UserLocal register is
implemented bit.
diffstat:
sys/arch/mips/include/mipsNN.h | 6 +++---
sys/arch/mips/mips/mips_machdep.c | 8 ++++----
2 files changed, 7 insertions(+), 7 deletions(-)
diffs (56 lines):
diff -r ee577e0383b7 -r c6153ba9549d sys/arch/mips/include/mipsNN.h
--- a/sys/arch/mips/include/mipsNN.h Sat Jun 13 14:31:49 2020 +0000
+++ b/sys/arch/mips/include/mipsNN.h Sat Jun 13 14:39:07 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsNN.h,v 1.6 2016/07/11 16:15:35 matt Exp $ */
+/* $NetBSD: mipsNN.h,v 1.7 2020/06/13 14:39:07 simonb Exp $ */
/*
* Copyright 2000, 2001
@@ -239,8 +239,8 @@
/* "CMGCR" (R): Coherency Manager memory-mapped Global Configuration Register Space is implemented. */
#define MIPSNN_CFG3_CMGCR 0x20000000
-/* "ULRP" (R): UserLocal register is implemented. */
-#define MIPSNN_CFG3_ULRP 0x00002000
+/* "ULRI" (R): UserLocal register is implemented. */
+#define MIPSNN_CFG3_ULRI 0x00002000
/* "IPLW" (R): Width of Status[IPL] and Cause[RIPL] fields. */
#define MIPSNN_CFG3_IPLW_MASK 0x00600000
diff -r ee577e0383b7 -r c6153ba9549d sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Sat Jun 13 14:31:49 2020 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Sat Jun 13 14:39:07 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.285 2020/06/10 01:42:17 simonb Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.286 2020/06/13 14:39:07 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -111,7 +111,7 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.285 2020/06/10 01:42:17 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.286 2020/06/13 14:39:07 simonb Exp $");
#define __INTR_PRIVATE
#include "opt_cputype.h"
@@ -935,7 +935,7 @@
uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags;
if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) {
const uint32_t cfg3 = mipsNN_cp0_config3_read();
- if (cfg3 & MIPSNN_CFG3_ULRP) {
+ if (cfg3 & MIPSNN_CFG3_ULRI) {
cp0flags |= MIPS_CP0FL_USERLOCAL;
}
if (cfg3 & MIPSNN_CFG3_DSP2P) {
@@ -1081,7 +1081,7 @@
uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags;
if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) {
const uint32_t cfg3 = mipsNN_cp0_config3_read();
- if (cfg3 & MIPSNN_CFG3_ULRP) {
+ if (cfg3 & MIPSNN_CFG3_ULRI) {
cp0flags |= MIPS_CP0FL_USERLOCAL;
}
if (cfg3 & MIPSNN_CFG3_DSP2P) {
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