[src/netbsd-9]: src/sys/arch/x86/x86 Pull up following revision(s) (requested...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a87340b2a187
branches:  netbsd-9
changeset: 934920:a87340b2a187
user:      martin <martin%NetBSD.org@localhost>
date:      Sat Jun 20 16:03:35 2020 +0000

description:
Pull up following revision(s) (requested by riastradh in ticket #960):

        sys/arch/x86/x86/cpu_rng.c: revision 1.16

Use x86_read_psl/x86_disable_intr/x86_read_psl to defer interrupts.

Using x86_disable_intr/x86_enable_intr causes a bit of a snag when we
try it early at boot before we're ready to handle interrupts, because
it has the effect of enabling interrupts!

Fixes instant reset at boot on VIA CPUs.  The instant reset on boot
is new since the entropy rework, which initialized the x86 CPU RNG
earlier than before, but in principle this could also cause other
problems while not early at boot too.

XXX pullup

diffstat:

 sys/arch/x86/x86/cpu_rng.c |  7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diffs (37 lines):

diff -r 19c22a23f279 -r a87340b2a187 sys/arch/x86/x86/cpu_rng.c
--- a/sys/arch/x86/x86/cpu_rng.c        Sat Jun 20 15:52:50 2020 +0000
+++ b/sys/arch/x86/x86/cpu_rng.c        Sat Jun 20 16:03:35 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_rng.c,v 1.9.4.1 2019/11/01 18:17:55 martin Exp $ */
+/* $NetBSD: cpu_rng.c,v 1.9.4.2 2020/06/20 16:03:35 martin Exp $ */
 
 /*-
  * Copyright (c) 2015 The NetBSD Foundation, Inc.
@@ -142,6 +142,7 @@
 static size_t
 cpu_rng_via(cpu_rng_t *out)
 {
+       u_long psl;
        uint32_t creg0, rndsts;
 
        /*
@@ -155,9 +156,9 @@
         * even if such a fault is generated.
         *
         * XXX can this really happen if we don't use "rep xstorrng"?
-        *
         */
        kpreempt_disable();
+       psl = x86_read_psl();
        x86_disable_intr();
        creg0 = rcr0();
        lcr0(creg0 & ~(CR0_EM|CR0_TS)); /* Permit access to SIMD/FPU path */
@@ -171,7 +172,7 @@
            : "=a" (rndsts), "+D" (out) : "d" (0) : "memory");
        /* Put CR0 back how it was */
        lcr0(creg0);
-       x86_enable_intr();
+       x86_write_psl(psl);
        kpreempt_enable();
 
        /*