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[src/trunk]: src/usr.sbin/cpuctl/arch show clidr_el1 and ctr_el0.
details: https://anonhg.NetBSD.org/src/rev/f51ee972f90d
branches: trunk
changeset: 935381:f51ee972f90d
user: ryo <ryo%NetBSD.org@localhost>
date: Wed Jul 01 08:03:10 2020 +0000
description:
show clidr_el1 and ctr_el0.
diffstat:
usr.sbin/cpuctl/arch/aarch64.c | 145 +++++++++++++++++++++++++++++++++++++---
1 files changed, 133 insertions(+), 12 deletions(-)
diffs (207 lines):
diff -r 2001b5cdc629 -r f51ee972f90d usr.sbin/cpuctl/arch/aarch64.c
--- a/usr.sbin/cpuctl/arch/aarch64.c Wed Jul 01 08:02:13 2020 +0000
+++ b/usr.sbin/cpuctl/arch/aarch64.c Wed Jul 01 08:03:10 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.9 2020/05/10 21:42:05 riastradh Exp $ */
+/* $NetBSD: aarch64.c,v 1.10 2020/07/01 08:03:10 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -29,7 +29,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.9 2020/05/10 21:42:05 riastradh Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.10 2020/07/01 08:03:10 ryo Exp $");
#endif /* no lint */
#include <sys/types.h>
@@ -60,8 +60,11 @@
};
struct fieldinfo {
- int bitpos;
- int bitwidth;
+ unsigned int flags;
+#define FIELDINFO_FLAGS_DEC 0x0001
+#define FIELDINFO_FLAGS_4LOG2 0x0002
+ unsigned char bitpos;
+ unsigned char bitwidth;
const char *name;
const char * const *info;
};
@@ -549,13 +552,108 @@
{ .bitwidth = 0 } /* end of table */
};
+/* CLIDR_EL1 - Cache Level ID Register */
+const char * const clidr_cachetype[8] = { /* 8=3bit */
+ [0] = "None",
+ [1] = "Instruction cache",
+ [2] = "Data cache",
+ [3] = "Instruction and Data cache",
+ [4] = "Unified cache"
+};
+
+struct fieldinfo clidr_fieldinfo[] = {
+ {
+ .bitpos = 0, .bitwidth = 3, .name = "L1",
+ .info = clidr_cachetype
+ },
+ {
+ .bitpos = 3, .bitwidth = 3, .name = "L2",
+ .info = clidr_cachetype
+ },
+ {
+ .bitpos = 6, .bitwidth = 3, .name = "L3",
+ .info = clidr_cachetype
+ },
+ {
+ .bitpos = 9, .bitwidth = 3, .name = "L4",
+ .info = clidr_cachetype
+ },
+ {
+ .bitpos = 12, .bitwidth = 3, .name = "L5",
+ .info = clidr_cachetype
+ },
+ {
+ .bitpos = 15, .bitwidth = 3, .name = "L6",
+ .info = clidr_cachetype
+ },
+ {
+ .bitpos = 18, .bitwidth = 3, .name = "L7",
+ .info = clidr_cachetype
+ },
+ {
+ .bitpos = 21, .bitwidth = 3, .name = "LoUU",
+ .flags = FIELDINFO_FLAGS_DEC
+ },
+ {
+ .bitpos = 24, .bitwidth = 3, .name = "LoC",
+ .flags = FIELDINFO_FLAGS_DEC
+ },
+ {
+ .bitpos = 27, .bitwidth = 3, .name = "LoUIS",
+ .flags = FIELDINFO_FLAGS_DEC
+ },
+ {
+ .bitpos = 30, .bitwidth = 3, .name = "ICB",
+ .flags = FIELDINFO_FLAGS_DEC
+ },
+ { .bitwidth = 0 } /* end of table */
+};
+
+struct fieldinfo ctr_fieldinfo[] = {
+ {
+ .bitpos = 0, .bitwidth = 4, .name = "IminLine",
+ .flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+ },
+ {
+ .bitpos = 16, .bitwidth = 4, .name = "DminLine",
+ .flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+ },
+ {
+ .bitpos = 14, .bitwidth = 2, .name = "L1 Icache policy",
+ .info = (const char *[4]) { /* 4=2bit */
+ [0] = "VMID aware PIPT (VPIPT)",
+ [1] = "ASID-tagged VIVT (AIVIVT)",
+ [2] = "VIPT",
+ [3] = "PIPT"
+ },
+ },
+ {
+ .bitpos = 20, .bitwidth = 4, .name = "ERG",
+ .flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+ },
+ {
+ .bitpos = 24, .bitwidth = 4, .name = "CWG",
+ .flags = FIELDINFO_FLAGS_DEC | FIELDINFO_FLAGS_4LOG2
+ },
+ {
+ .bitpos = 28, .bitwidth = 1, .name = "DIC",
+ .flags = FIELDINFO_FLAGS_DEC
+ },
+ {
+ .bitpos = 29, .bitwidth = 1, .name = "IDC",
+ .flags = FIELDINFO_FLAGS_DEC
+ },
+ { .bitwidth = 0 } /* end of table */
+};
+
+
static void
print_fieldinfo(const char *cpuname, const char *setname,
struct fieldinfo *fieldinfo, uint64_t data)
{
uint64_t v;
const char *info;
- int i;
+ int i, flags;
#define WIDTHMASK(w) (0xffffffffffffffffULL >> (64 - (w)))
@@ -563,13 +661,24 @@
v = (data >> fieldinfo[i].bitpos) &
WIDTHMASK(fieldinfo[i].bitwidth);
- info = fieldinfo[i].info[v];
- if (info == NULL)
- printf("%s: %s: %s: 0x%"PRIx64"\n",
- cpuname, setname, fieldinfo[i].name, v);
- else
- printf("%s: %s: %s: %s\n",
- cpuname, setname, fieldinfo[i].name, info);
+ flags = fieldinfo[i].flags;
+ info = NULL;
+ if (fieldinfo[i].info != NULL)
+ info = fieldinfo[i].info[v];
+
+ printf("%s: %s: %s: ",
+ cpuname, setname, fieldinfo[i].name);
+
+ if (info == NULL) {
+ if (flags & FIELDINFO_FLAGS_4LOG2)
+ v = 4 * (1 << v);
+ if (flags & FIELDINFO_FLAGS_DEC)
+ printf("%"PRIu64"\n", v);
+ else
+ printf("0x%"PRIx64"\n", v);
+ } else {
+ printf("%s\n", info);
+ }
}
}
@@ -671,6 +780,7 @@
snprintf(path, sizeof path, "machdep.%s.cpu_id", cpuname);
len = sizeof(sysctlbuf);
+ memset(sysctlbuf, 0, len);
if (sysctlbyname(path, id, &len, 0, 0) == -1)
err(1, "couldn't get %s", path);
if (len != sizeof(struct aarch64_sysctl_cpu_id))
@@ -707,6 +817,10 @@
cpuname, id->ac_mvfr1);
printf("%s: MVFR2_EL1: 0x%08"PRIx32"\n",
cpuname, id->ac_mvfr2);
+ printf("%s: CLIDR_EL1: 0x%016"PRIx64"\n",
+ cpuname, id->ac_clidr);
+ printf("%s: CTR_EL0: 0x%016"PRIx64"\n",
+ cpuname, id->ac_ctr);
}
identify_midr(cpuname, id->ac_midr);
@@ -730,6 +844,13 @@
mvfr1_fieldinfo, id->ac_mvfr1);
print_fieldinfo(cpuname, "media and VFP features 2",
mvfr2_fieldinfo, id->ac_mvfr2);
+
+ if (len <= offsetof(struct aarch64_sysctl_cpu_id, ac_clidr))
+ return;
+ print_fieldinfo(cpuname, "cache level",
+ clidr_fieldinfo, id->ac_clidr);
+ print_fieldinfo(cpuname, "cache type",
+ ctr_fieldinfo, id->ac_ctr);
}
bool
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