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[src/netbsd-9]: src/sys/dev/pci Pull up the following revisions, requested by...
details: https://anonhg.NetBSD.org/src/rev/d5a13a4d98f6
branches: netbsd-9
changeset: 936016:d5a13a4d98f6
user: martin <martin%NetBSD.org@localhost>
date: Wed Jul 15 17:16:59 2020 +0000
description:
Pull up the following revisions, requested by msaitoh in ticket #1014:
sys/dev/pci/if_ti.c 1.116-1.120 via patch
sys/dev/pci/if_tireg.h 1.26
- Don't clear CFI and priority bit to pass them to the upper layer.
- Add support for Farallon PN9000SX from FreeBSD.
- Fix typo in comment.
- Style fix.
diffstat:
sys/dev/pci/if_ti.c | 28 ++++++++++++++--------------
sys/dev/pci/if_tireg.h | 4 ++--
2 files changed, 16 insertions(+), 16 deletions(-)
diffs (130 lines):
diff -r 9cca61f303e0 -r d5a13a4d98f6 sys/dev/pci/if_ti.c
--- a/sys/dev/pci/if_ti.c Wed Jul 15 15:52:24 2020 +0000
+++ b/sys/dev/pci/if_ti.c Wed Jul 15 17:16:59 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_ti.c,v 1.112 2019/07/09 08:46:59 msaitoh Exp $ */
+/* $NetBSD: if_ti.c,v 1.112.2.1 2020/07/15 17:16:59 martin Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -81,7 +81,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.112 2019/07/09 08:46:59 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.112.2.1 2020/07/15 17:16:59 martin Exp $");
#include "opt_inet.h"
@@ -140,6 +140,8 @@
"Netgear GA620 1000BASE-T Ethernet" },
{ PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON,
"Silicon Graphics Gigabit Ethernet" },
+ { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PN9000SX,
+ "Farallon PN9000SX Gigabit Ethernet" },
{ 0, 0, NULL }
};
@@ -216,7 +218,7 @@
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
/*
- * Feed in each bit and stobe the clock.
+ * Feed in each bit and strobe the clock.
*/
for (i = 0x80; i; i >>= 1) {
if (byte & i) {
@@ -762,7 +764,7 @@
}
/*
- * Intialize a mini receive ring descriptor. This only applies to
+ * Initialize a mini receive ring descriptor. This only applies to
* the Tigon 2.
*/
static int
@@ -903,7 +905,7 @@
for (i = 0; i < TI_SSLOTS; i++) {
if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
return (ENOBUFS);
- };
+ }
TI_UPDATE_STDPROD(sc, i - 1);
sc->ti_std = i - 1;
@@ -941,7 +943,7 @@
for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
return (ENOBUFS);
- };
+ }
TI_UPDATE_JUMBOPROD(sc, i - 1);
sc->ti_jumbo = i - 1;
@@ -974,7 +976,7 @@
for (i = 0; i < TI_MSLOTS; i++) {
if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS)
return (ENOBUFS);
- };
+ }
TI_UPDATE_MINIPROD(sc, i - 1);
sc->ti_mini = i - 1;
@@ -2026,10 +2028,8 @@
break;
}
- if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
- /* ti_vlan_tag also has the priority, trim it */
- vlan_set_tag(m, cur_rx->ti_vlan_tag & 0x0fff);
- }
+ if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG)
+ vlan_set_tag(m, cur_rx->ti_vlan_tag);
if_percpuq_enqueue(ifp->if_percpuq, m);
}
@@ -2205,7 +2205,7 @@
}
/*
- * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
+ * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
* pointers to descriptors.
*/
static int
@@ -2684,7 +2684,7 @@
static int
ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data)
{
- struct ifaddr *ifa = (struct ifaddr *) data;
+ struct ifaddr *ifa = (struct ifaddr *)data;
struct ti_softc *sc = ifp->if_softc;
if ((ifp->if_flags & IFF_UP) == 0) {
@@ -2717,7 +2717,7 @@
ti_ioctl(struct ifnet *ifp, u_long command, void *data)
{
struct ti_softc *sc = ifp->if_softc;
- struct ifreq *ifr = (struct ifreq *) data;
+ struct ifreq *ifr = (struct ifreq *)data;
int s, error = 0;
struct ti_cmd_desc cmd;
diff -r 9cca61f303e0 -r d5a13a4d98f6 sys/dev/pci/if_tireg.h
--- a/sys/dev/pci/if_tireg.h Wed Jul 15 15:52:24 2020 +0000
+++ b/sys/dev/pci/if_tireg.h Wed Jul 15 17:16:59 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_tireg.h,v 1.21 2019/03/05 08:25:02 msaitoh Exp $ */
+/* $NetBSD: if_tireg.h,v 1.21.4.1 2020/07/15 17:16:59 martin Exp $ */
/*
* Copyright (c) 1997, 1998, 1999
@@ -39,7 +39,7 @@
* which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
* Each register must be accessed using 32 bit operations.
*
- * All reegisters are accessed through a 16K shared memory block.
+ * All registers are accessed through a 16K shared memory block.
* The first group of registers are actually copies of the PCI
* configuration space registers.
*/
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