[src/trunk]: src/sys/arch/mips/cavium Fix confusion between ipi bitmask and m...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1abf6d263374
branches:  trunk
changeset: 936158:1abf6d263374
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Mon Jul 20 13:30:41 2020 +0000

description:
Fix confusion between ipi bitmask and mbox register bit assignments.

diffstat:

 sys/arch/mips/cavium/octeon_intr.c |  28 +++++++++++++++++-----------
 1 files changed, 17 insertions(+), 11 deletions(-)

diffs (70 lines):

diff -r a81e6588def3 -r 1abf6d263374 sys/arch/mips/cavium/octeon_intr.c
--- a/sys/arch/mips/cavium/octeon_intr.c        Mon Jul 20 10:53:47 2020 +0000
+++ b/sys/arch/mips/cavium/octeon_intr.c        Mon Jul 20 13:30:41 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $        */
+/*     $NetBSD: octeon_intr.c,v 1.19 2020/07/20 13:30:41 jmcneill Exp $        */
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
@@ -44,7 +44,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.18 2020/07/17 21:59:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.19 2020/07/20 13:30:41 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -176,7 +176,7 @@
 #define        OCTEON_IPI_SCHED(n)     __BIT((n) + 0)
 #define        OCTEON_IPI_HIGH(n)      __BIT((n) + 16)
 
-static uint64_t octeon_ipi_mask[NIPIS] = {
+static uint32_t octeon_ipi_mbox_mask[NIPIS] = {
        [IPI_NOP]               = OCTEON_IPI_SCHED(IPI_NOP),
        [IPI_AST]               = OCTEON_IPI_SCHED(IPI_AST),
        [IPI_SHOOTDOWN]         = OCTEON_IPI_SCHED(IPI_SHOOTDOWN),
@@ -516,16 +516,21 @@
 {
        struct cpu_info * const ci = curcpu();
        struct cpu_softc * const cpu = ci->ci_softc;
-       uint32_t ipi_mask = (uintptr_t) arg;
+       uint32_t mbox_mask = (uintptr_t) arg;
+       uint32_t ipi_mask;
 
-       KASSERTMSG((ipi_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
-           "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
+       KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
+           "mbox_mask %#"PRIx32" cpl %d", mbox_mask, ci->ci_cpl);
 
-       ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
-       if (ipi_mask == 0)
+       mbox_mask &= mips3_ld(cpu->cpu_mbox_set);
+       if (mbox_mask == 0)
                return 0;
 
-       mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
+       mips3_sd(cpu->cpu_mbox_clr, mbox_mask);
+
+       ipi_mask = mbox_mask;
+       if (ci->ci_cpl >= IPL_SCHED)
+               ipi_mask >>= 16;
 
        KASSERT(ipi_mask < __BIT(NIPIS));
 
@@ -573,11 +578,12 @@
                return -1;
 
        struct cpu_softc * const cpu = ci->ci_softc;
-       const uint64_t ipi_mask = octeon_ipi_mask[req];
+       const uint32_t mbox_mask = octeon_ipi_mbox_mask[req];
+       const uint32_t ipi_mask = __BIT(req);
 
        atomic_or_64(&ci->ci_request_ipis, ipi_mask);
 
-       mips3_sd(cpu->cpu_mbox_set, ipi_mask);
+       mips3_sd(cpu->cpu_mbox_set, mbox_mask);
 
        return 0;
 }