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[src/trunk]: src/sys/arch/mips/mips Add all the Cavium Networks cpu ids



details:   https://anonhg.NetBSD.org/src/rev/a497a50cacf9
branches:  trunk
changeset: 936701:a497a50cacf9
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sun Aug 02 06:51:47 2020 +0000

description:
Add all the Cavium Networks cpu ids

diffstat:

 sys/arch/mips/mips/cache.c |  7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diffs (38 lines):

diff -r c8a30efa7043 -r a497a50cacf9 sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c        Sun Aug 02 01:36:46 2020 +0000
+++ b/sys/arch/mips/mips/cache.c        Sun Aug 02 06:51:47 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $       */
+/*     $NetBSD: cache.c,v 1.68 2020/08/02 06:51:47 skrll Exp $ */
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.68 2020/08/02 06:51:47 skrll Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -1413,9 +1413,11 @@
                        break;
 
                /* XXX cnMIPS II cores not yet tested */
+               case MIPS_CN61XX:
                case MIPS_CN63XX:
                case MIPS_CN66XX:
                case MIPS_CN68XX:
+               case MIPS_CNF71XX:
                        /* OCTEON II */
 
                        mci->mci_pdcache_line_size = OCTEON_CACHELINE_SIZE;
@@ -1432,6 +1434,7 @@
 
                case MIPS_CN70XX:
                case MIPS_CN73XX:
+               case MIPS_CNF75XX:
                case MIPS_CN78XX:
                        /* OCTEON III */
 



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