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[src-draft/trunk]: src/sys/dev/usb Add bb_write function with a default delay...
details: https://anonhg.NetBSD.org/src-all/rev/6a539e0b37a7
branches: trunk
changeset: 939902:6a539e0b37a7
user: Nathanial Sloss <nat%netbsd.org@localhost>
date: Fri Aug 14 03:32:27 2020 +1000
description:
Add bb_write function with a default delay of one microsecond.
Remove the rest of unnecessary delays after a bb_write.
diffstat:
sys/dev/usb/if_urtwn.c | 61 ++++++-------------------------------------------
1 files changed, 8 insertions(+), 53 deletions(-)
diffs (truncated from 315 to 300 lines):
diff -r 0cd04a5e0306 -r 6a539e0b37a7 sys/dev/usb/if_urtwn.c
--- a/sys/dev/usb/if_urtwn.c Fri Aug 14 03:14:50 2020 +1000
+++ b/sys/dev/usb/if_urtwn.c Fri Aug 14 03:32:27 2020 +1000
@@ -247,6 +247,7 @@
static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t);
static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t);
static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t);
+static void urtwn_bb_write(struct urtwn_softc *, uint16_t, uint32_t);
static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *,
int);
static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *,
@@ -350,7 +351,6 @@
//static int urtwn_send_mgmt(struct ieee80211_node *, int, int);
/* Aliases. */
-#define urtwn_bb_write urtwn_write_4
#define urtwn_bb_read urtwn_read_4
#define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p))
@@ -1048,6 +1048,13 @@
tsleep(&sc->cmdq, 0, "endtask", 0);
}
+static void
+urtwn_bb_write(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
+{
+ urtwn_write_4(sc, addr, val);
+ DELAY(1);
+}
+
static int
urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
int len)
@@ -2447,7 +2454,6 @@
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
- urtwn_delay_ms(sc, 1);
if (!ISSET(sc->chip, URTWN_CHIP_88E)) {
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
@@ -2455,7 +2461,6 @@
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
}
- urtwn_delay_ms(sc, 1);
/* Set media status to 'No Link'. */
urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
@@ -4624,7 +4629,6 @@
break;
}
urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
- DELAY(1);
}
if (sc->chip & URTWN_CHIP_92C_1T2R) {
@@ -4632,62 +4636,49 @@
reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
reg = (reg & ~0x00000003) | 0x2;
urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
reg = (reg & ~0x00300033) | 0x00200022;
urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
reg = (reg & ~0xff000000) | (0x45 << 24);
urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
reg = (reg & ~0x000000ff) | 0x23;
urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
reg = (reg & ~0x00000030) | (1 << 4);
urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe74);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe74, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe78);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe78, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe7c);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe7c, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe80);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe80, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0xe88);
reg = (reg & ~0x0c000000) | (2 << 26);
urtwn_bb_write(sc, 0xe88, reg);
- urtwn_delay_ms(sc, 1);
}
/* Write AGC values. */
for (i = 0; i < prog->agccount; i++) {
urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]);
- DELAY(1);
}
if (ISSET(sc->chip, URTWN_CHIP_88E) ||
ISSET(sc->chip, URTWN_CHIP_92EU)) {
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
- DELAY(1);
urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
- DELAY(1);
}
if (ISSET(sc->chip, URTWN_CHIP_92EU)) {
@@ -4710,7 +4701,6 @@
urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
crystalcap | crystalcap << 6));
- urtwn_delay_ms(sc, 1);
} else {
if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
R92C_HSSI_PARAM2_CCK_HIPWR) {
@@ -4945,26 +4935,22 @@
reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
- urtwn_delay_ms(sc, 1);
} else {
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
- urtwn_delay_ms(sc, 1);
}
/* Write per-OFDM rate Tx power. */
urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
@@ -4972,38 +4958,32 @@
SM(R92C_TXAGC_RATE09, power[ 5]) |
SM(R92C_TXAGC_RATE12, power[ 6]) |
SM(R92C_TXAGC_RATE18, power[ 7]));
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
SM(R92C_TXAGC_RATE24, power[ 8]) |
SM(R92C_TXAGC_RATE36, power[ 9]) |
SM(R92C_TXAGC_RATE48, power[10]) |
SM(R92C_TXAGC_RATE54, power[11]));
- urtwn_delay_ms(sc, 1);
/* Write per-MCS Tx power. */
urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
SM(R92C_TXAGC_MCS00, power[12]) |
SM(R92C_TXAGC_MCS01, power[13]) |
SM(R92C_TXAGC_MCS02, power[14]) |
SM(R92C_TXAGC_MCS03, power[15]));
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
SM(R92C_TXAGC_MCS04, power[16]) |
SM(R92C_TXAGC_MCS05, power[17]) |
SM(R92C_TXAGC_MCS06, power[18]) |
SM(R92C_TXAGC_MCS07, power[19]));
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
SM(R92C_TXAGC_MCS08, power[20]) |
SM(R92C_TXAGC_MCS09, power[21]) |
SM(R92C_TXAGC_MCS10, power[22]) |
SM(R92C_TXAGC_MCS11, power[23]));
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
SM(R92C_TXAGC_MCS12, power[24]) |
SM(R92C_TXAGC_MCS13, power[25]) |
SM(R92C_TXAGC_MCS14, power[26]) |
SM(R92C_TXAGC_MCS15, power[27]));
- urtwn_delay_ms(sc, 1);
}
static void
@@ -5253,31 +5233,25 @@
urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
- urtwn_delay_ms(sc, 1);
/* Set CCK side band. */
reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
~R92C_FPGA0_ANAPARAM2_CBW20);
- urtwn_delay_ms(sc, 1);
reg = urtwn_bb_read(sc, 0x818);
reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
urtwn_bb_write(sc, 0x818, reg);
- urtwn_delay_ms(sc, 1);
/* Select 40MHz bandwidth. */
urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
@@ -5288,10 +5262,8 @@
urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
- urtwn_delay_ms(sc, 1);
if (!ISSET(sc->chip, URTWN_CHIP_88E) &&
!ISSET(sc->chip, URTWN_CHIP_92EU)) {
@@ -5382,7 +5354,6 @@
for (i = 0; i < __arraycount(addaReg); i++) {
urtwn_bb_write(sc, addaReg[i],
addaReg[__arraycount(addaReg) - 1]);
- urtwn_delay_ms(sc, 1);
}
urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc,
R92C_CCK0_AFESETTING));
@@ -5394,7 +5365,6 @@
if (sc->ntxchains > 1)
urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM);
- urtwn_delay_ms(sc, 1);
urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL);
urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] &
~R92C_BCN_CTRL_EN_BCN));
@@ -5405,33 +5375,22 @@
~R92C_GPIO_MUXCFG_ENBT));
urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT);
- urtwn_delay_ms(sc, 1);
if (sc->ntxchains > 1)
urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING);
- urtwn_delay_ms(sc, 1);
/* Restore BB regs. */
urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0);
- urtwn_delay_ms(sc, 1);
urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE);
- urtwn_delay_ms(sc, 1);
if (sc->nrxchains > 1)
urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE);
- urtwn_delay_ms(sc, 1);
if (attempt-- > 0)
goto next_attempt;
@@ -5458,7 +5417,6 @@
/* Restore adda regs. */
for (i = 0; i < __arraycount(addaReg); i++)
urtwn_bb_write(sc, addaReg[i], addaBackup[i]);
- urtwn_delay_ms(sc, 1);
/* Restore mac regs. */
urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]);
urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]);
@@ -5748,11 +5706,9 @@
reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
reg |= R92C_RFMOD_CCK_EN;
urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
- urtwn_delay_ms(sc, 1);
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