[src/trunk]: src/sys/arch/arm/rockchip rk3399_pcie: do reset timing according...

[tnn <tnn%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f33bd787ad54
branches:  trunk
changeset: 940516:f33bd787ad54
user:      tnn <tnn%NetBSD.org@localhost>
date:      Thu Oct 08 22:14:00 2020 +0000

description:
rk3399_pcie: do reset timing according to PCI Express Base Specification

Don't do link training or configuration space accesses within the time
allowed by the standard for the downstream card to come out of reset
after deasserting PERST#.

This fixes detection issues seen with a dual port wm(4) NIC,
an ASMedia SATA card and also Pericom bridges (but they need more work
to be useful).

diffstat:

 sys/arch/arm/rockchip/rk3399_pcie.c |  12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diffs (50 lines):

diff -r 729ad94ca8db -r f33bd787ad54 sys/arch/arm/rockchip/rk3399_pcie.c
--- a/sys/arch/arm/rockchip/rk3399_pcie.c       Thu Oct 08 21:00:25 2020 +0000
+++ b/sys/arch/arm/rockchip/rk3399_pcie.c       Thu Oct 08 22:14:00 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399_pcie.c,v 1.10 2020/06/17 06:51:08 thorpej Exp $ */
+/* $NetBSD: rk3399_pcie.c,v 1.11 2020/10/08 22:14:00 tnn Exp $ */
 /*
  * Copyright (c) 2018 Mark Kettenis <kettenis%openbsd.org@localhost>
  *
@@ -17,7 +17,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.10 2020/06/17 06:51:08 thorpej Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.11 2020/10/08 22:14:00 tnn Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -278,7 +278,7 @@
        reset_assert(phandle, "mgmt-sticky");
        reset_assert(phandle, "pipe");
 
-       delay(10);
+       delay(1000);    /* TPERST. use 1ms */
        
        reset_deassert(phandle, "pm");
        reset_deassert(phandle, "aclk");
@@ -311,11 +311,12 @@
        reset_deassert(phandle, "mgmt");
        reset_deassert(phandle, "pipe");
 
+       fdtbus_gpio_write(ep_gpio, 1);
+       delay(20000);   /* 20 ms according to PCI-e BS "Conventional Reset" */
+
        /* Start link training. */
        HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN);
 
-       fdtbus_gpio_write(ep_gpio, 1);
-
        for (timo = 500; timo > 0; timo--) {
                status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1);
                if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE)
@@ -346,6 +347,7 @@
                        goto again;
                }
        }
+       delay(80000);   /* wait 100 ms before CSR access. already waited 20. */
 
        fdtbus_gpio_release(ep_gpio);