[src/trunk]: src/sys/arch/arm/arm32 Sprinkle some comments about ENABLE_ALIGN...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/dc022c65bdd1
branches:  trunk
changeset: 946244:dc022c65bdd1
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sat Nov 21 19:46:13 2020 +0000

description:
Sprinkle some comments about ENABLE_ALIGNMENT_FAULTS leaving curcpu in r4
and curlwp in r5

diffstat:

 sys/arch/arm/arm32/exception.S    |  12 ++++++------
 sys/arch/arm/arm32/irq_dispatch.S |   7 ++++---
 2 files changed, 10 insertions(+), 9 deletions(-)

diffs (82 lines):

diff -r db07fb7e879c -r dc022c65bdd1 sys/arch/arm/arm32/exception.S
--- a/sys/arch/arm/arm32/exception.S    Sat Nov 21 19:44:52 2020 +0000
+++ b/sys/arch/arm/arm32/exception.S    Sat Nov 21 19:46:13 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: exception.S,v 1.25 2019/08/11 06:49:31 skrll Exp $     */
+/*     $NetBSD: exception.S,v 1.26 2020/11/21 19:46:13 skrll Exp $     */
 
 /*
  * Copyright (c) 1994-1997 Mark Brinicombe.
@@ -51,7 +51,7 @@
 
 #include <arm/locore.h>
 
-       RCSID("$NetBSD: exception.S,v 1.25 2019/08/11 06:49:31 skrll Exp $")
+       RCSID("$NetBSD: exception.S,v 1.26 2020/11/21 19:46:13 skrll Exp $")
 
        .text
        .align  0
@@ -80,7 +80,7 @@
  */
 ARM_ASENTRY_NP(swi_entry)
        PUSHFRAME
-       ENABLE_ALIGNMENT_FAULTS
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
        mov     r0, sp                  /* Pass the frame to any function */
        bl      _C_LABEL(swi_handler)   /* It's a SWI ! */
@@ -111,7 +111,7 @@
        clrex
 #endif
        PUSHFRAMEINSVC
-       ENABLE_ALIGNMENT_FAULTS
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
        ldr     r1, .Lprefetch_abort_handler_address
        adr     lr, .Lexception_exit
@@ -158,7 +158,7 @@
 #endif
        PUSHFRAMEINSVC                  /* Push trap frame and switch */
                                        /* to SVC32 mode */
-       ENABLE_ALIGNMENT_FAULTS
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
        ldr     r1, .Ldata_abort_handler_address
        adr     lr, .Lexception_exit
@@ -261,7 +261,7 @@
        PUSHXXXREGSANDSWITCH
        PUSHDTRACEGAP
        PUSHTRAPFRAME(r2)
-       ENABLE_ALIGNMENT_FAULTS
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
        mov     r0, sp
        adr     lr, .Lexception_exit
diff -r db07fb7e879c -r dc022c65bdd1 sys/arch/arm/arm32/irq_dispatch.S
--- a/sys/arch/arm/arm32/irq_dispatch.S Sat Nov 21 19:44:52 2020 +0000
+++ b/sys/arch/arm/arm32/irq_dispatch.S Sat Nov 21 19:46:13 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: irq_dispatch.S,v 1.16 2015/06/02 14:06:16 matt Exp $   */
+/*     $NetBSD: irq_dispatch.S,v 1.17 2020/11/21 19:46:13 skrll Exp $  */
 
 /*
  * Copyright (c) 2002 Fujitsu Component Limited
@@ -95,7 +95,7 @@
        sub     lr, lr, #0x00000004     /* Adjust the lr */
 
        PUSHFRAMEINSVC                  /* Push an interrupt frame */
-       ENABLE_ALIGNMENT_FAULTS         /* finishes with curcpu() in r4 */
+       ENABLE_ALIGNMENT_FAULTS         /* puts cur{cpu,lwp} in r4/r5 */
 
 #ifdef _ARM_ARCH_7
        clrex                           /* force all strex to fail */
@@ -108,7 +108,8 @@
         * callee-saved regs here.  We use the following registers, which
         * we expect to persist:
         *
-        *      r4      address of current cpu_info
+        *      r4      address of current cpu_info (curcpu)
+        *      r5      address of current lwp (curlwp)
         *      r6      old value of `ci_intr_depth'
         */
        ldr     r6, [r4, #CI_INTR_DEPTH]